SH79F024XU datasheet(30/92 Pages) SINOWEALTH

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SH79F

SH79F082

082

7.7

7.7 Timer

Timer

7.7.1

7.7.1 Feature

Feature

�

The SH79F082 has two timers (Timer0, 1) which are compatible with the standard 8051

�

Timer 0 is compatible with the standard 8051

�

Timer 1 is compatible with the standard 8051

�

Timer0 compare function

7.7.2

7.7.2 Timer

Timer

Timer 0,

0, 1

Each timer is implemented as a 16-bit register accessed as two cascaded Timer x/Counter x Data Registers: THx & TLx (x =

0, 1). They are controlled by the register TCON and TMOD. The Timer 0 & Timer 1 interrupts can be enabled by setting the

ET0 & ET1 bit in the IEN0 register (Refer to Interrupt Section for details).

7.7.3

7.7.3 Timer

Timer

Timer x

x Mode

Mode

Mode (x

(x =

= 0,

0, 1)

Both timers operate in one of four primary modes selected by the Mode Select bits Mx1-Mx0 (x = 0, 1) in the Counter/Timer

Mode register (TMOD).

Mode

Mode 0:

0: 13-bit

13-bit

13-bit Counter/Timer

Counter/Timer

Timer x operate as 13-bit counter/timers in Mode 0. The THx register holds the high eight bits of the 13-bit counter/timer, TLx

holds the five low bits TLx.4 - TLx.0. The three upper bits (TLx.7 - TLx.5) of TLx are indeterminate and should be ignored

when reading. As the 13-bit timer register increments and overflows, the timer overflow flag TFx is set and an interrupt will

occur if Timer interrupts is enabled. The C/ T0

———

bit selects the counter/timer's clock source, timer1 do not have counter intput

source. so timer1 can not work when C/T1

———

= 1.

If C/ T0

———

= 1, high-to-low transitions at the Timer input pin (T0) will increase the timer/Counter Data register. Else if C/ T0

———

= 0,

selects the system clock to increase the timer/Counter Data register. Timer1 do not have T1 pin, if C/ T1

———

= 1, timer1 can not

work.

Setting the TRx bit enables the timer when either GATEx = 0, or GATEx = 1 and the input signal INTx

————

is active. Setting

GATEx to ‘1’ allows the timer to be controlled by the external input signal INTx

————

, facilitating positive pulse width in INTx

————

measurements. Setting TRx does not force the timer to reset. This means that if TRx is set, the timer register will count from

the old value that was last stopped by clearing TRx. So the timer registers should be loaded with the desired initial value

before the timer is enabled.

When as Timer, the T0 pin can automatically toggle upon Timer0 overflow by configuring TC0 in TCON1 Register. The T0

pin is automatically set as output by hardware when TC0 is set. Timer1 do not have compare function.

TLx

(5bits)

THx

(8bits)

TFx

Overflow

GATEx

INTx

TRx

C/Tx

0:Switch Off

1:Switch On

The Block Diagram of mode0 of Timerx ( x=0,1 )

Interrupt

Request

Overflow

Flag

System Clock

C/Tx=0 and TCx=1

Note:

Note: Tx (x = 0), timer1 without T1 pin.

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