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SH79F024XU bảng dữ liệu(PDF) 64 Page - SINOWEALTH Electronic Ltd |
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SH79F024XU bảng dữ liệu(HTML) 64 Page - SINOWEALTH Electronic Ltd |
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64 / 92 page  SH79F SH79F SH79F SH79F082 082 082 082 64 EUART EUART EUART EUART R R R Related elated elated elated SFR SFR SFR SFR Table Table Table Table 8 8 8 8....17 17 17 17 EUART Control & Status Register 9 9 9 98 8 8 8H H H H Bit7 Bit7 Bit7 Bit7 Bit6 Bit6 Bit6 Bit6 Bit5 Bit5 Bit5 Bit5 Bit4 Bit4 Bit4 Bit4 Bit3 Bit3 Bit3 Bit3 Bit2 Bit2 Bit2 Bit2 Bit1 Bit1 Bit1 Bit1 Bit0 Bit0 Bit0 Bit0 S S S SCON CON CON CON SM0/FE SM1/RXOV SM2/TXCOL REN TB8 RB8 TI RI R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Reset Reset Reset Value Value Value Value ((((POR/WDT/LVR POR/WDT/LVR POR/WDT/LVR POR/WDT/LVR/PIN /PIN /PIN /PIN)))) 0 0 0 0 0 0 0 0 Bit Bit Bit Bit Number Number Number Number Bit Bit Bit Bit Mnemonic Mnemonic Mnemonic Mnemonic Description Description Description Description 7-6 7-6 7-6 7-6 SM[ SM[ SM[ SM[0 0 0 0:1] :1] :1] :1] EUART EUART EUART EUART Serial Serial Serial Serial mode mode mode mode control control control control bit bit bit bit,,,, when when when when SST SST SST SSTA A A AT T T T = = = = 0 0 0 0 00: mode 0, Synchronous Mode, fixed baud rate 01: mode 1, 8 bit Asynchronous Mode, variable baud rate 10: mode 2, 9 bit Asynchronous Mode, fixed baud rate 11: mode 3, 9 bit Asynchronous Mode, variable baud rate 7 7 7 7 FE FE FE FE EUART EUART EUART EUART Frame Frame Frame Frame Error Error Error Error flag, flag, flag, flag, when when when when FE FE FE FE bit bit bit bit is is is is read read read read，SSTAT SSTAT SSTAT SSTAT bit bit bit bit must must must must be be be be set set set set 1 1 1 1 0: No Frame Error, clear by software 1: Frame error occurs, set by hardware 6 6 6 6 RXOV RXOV RXOV RXOV EUART EUART EUART EUART Receive Receive Receive Receive Over Over Over Over flag, flag, flag, flag, when when when when RXOV RXOV RXOV RXOV bit bit bit bit is is is is read read read read,,,, SSTAT SSTAT SSTAT SSTAT bit bit bit bit must must must must be be be be set set set set 1 1 1 1 0: No Receive Over, clear by software 1: Receive over occurs, set by hardware 5 5 5 5 SM2 SM2 SM2 SM2 EUART EUART EUART EUART Multi-processor Multi-processor Multi-processor Multi-processor communication communication communication communication enable enable enable enable bit bit bit bit (9 (9 (9 (9th th th th bit bit bit bit ‘‘‘‘1 1 1 1’’’’ checker), checker), checker), checker), when when when when SSTAT SSTAT SSTAT SSTAT = = = = 0 0 0 0 0: In mode 0, baud-rate is 1/12 of system clock In mode 1, disable stop bit validation check, any stop bit will set RI to generate interrupt In mode 2 & 3, any byte will set RI to generate interrupt 1: In mode 0, baud-rate is 1/4 of system clock In mode 1, Enable stop bit validation check, only valid stop bit (1) will set RI to generate interrupt In mode 2 & 3, only address byte (9th bit = 1) will set RI to generate interrupt 5 5 5 5 TXCOL TXCOL TXCOL TXCOL EUART EUART EUART EUART Transmit Transmit Transmit Transmit Collision Collision Collision Collision flag, flag, flag, flag, when when when when T T T TX X X XC C C CO O O OL L L L bit bit bit bit is is is is read read read read,,,, SSTAT SSTAT SSTAT SSTAT bit bit bit bit must must must must be be be be set set set set 1 1 1 1 0: No Transmit Collision, clear by software 1: Transmit Collision occurs, set by hardware 4 4 4 4 REN REN REN REN EUART EUART EUART EUART Receiver Receiver Receiver Receiver enable enable enable enable bit bit bit bit 0: Receive Disable 1: Receive Enable 3 3 3 3 TB8 TB8 TB8 TB8 T T T The he he he 9th 9th 9th 9th bit bit bit bit to to to to be be be be transmitted transmitted transmitted transmitted in in in in mode mode mode mode 2 2 2 2 & & & & 3 3 3 3 of of of of EUART, EUART, EUART, EUART, set set set set or or or or clear clear clear clear by by by by software software software software 2 2 2 2 RB8 RB8 RB8 RB8 T T T The he he he 9th 9th 9th 9th bit bit bit bit to to to to be be be be receiv receiv receiv received ed ed ed in in in in mode mode mode mode 1, 1, 1, 1,2 2 2 2 & & & & 3 3 3 3 of of of of EUART EUART EUART EUART In mode 0, RB8 is not used In mode 1, if receive interrupt occurs, RB8 is the stop bit that was received In modes 2 & 3 it is the 9th bit that was received 1 1 1 1 TI TI TI TI Transmit Transmit Transmit Transmit interrupt interrupt interrupt interrupt flag flag flag flag of of of of EUART EUART EUART EUART 0: cleared by software 1: Set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in other modes 0 0 0 0 RI RI RI RI Receive Receive Receive Receive interrupt interrupt interrupt interrupt flag flag flag flag of of of of EUART EUART EUART EUART 0: cleared by software. 1: Set by hardware at the end of the 8th bit time in mode 0, or during the stop bit time in other modes |
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