MSP432P411VIPZ datasheet(127/212 Pages) TI1

127 / 212 page

127

MSP432P4111, MSP432P4011, MSP432P411Y

MSP432P401Y, MSP432P411V, MSP432P401V

www.ti.com

SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018

Submit Documentation Feedback

Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V

Detailed Description

NOTE

Software must make sure that DMA_INT1, DMA_INT2, and DMA_INT3 are mapped to

different channels, so that the same channel does not result in multiple interrupts at the

NVIC.

6.5.3

DMA Access Privileges

The DMA has access to all of the memories and peripheral configuration interfaces of the device. If the

device is configured for IP protection, DMA access to the flash is restricted to only bank 1 of the flash

main and information memory regions. This restriction prevents the DMA from being used as an

unauthorized access source into bank 0 of the flash, where secure data regions are housed.

6.6

Memory Map Access Details

The bus system on MSP432P4x1x devices incorporates four masters, which can initiate various types of

transactions:

•

ICODE: Cortex-M4 instruction fetch bus. Accesses the Code zone only

•

DCODE: Cortex-M4 data and literal load/store bus. Accesses the Code zone only. Debugger accesses

to Code zone also appear on this bus.

•

SBUS: Cortex-M4 data read and write bus. Accesses to all zones except Code zones and PPB

memory space only. Debugger accesses to this space also appear on this bus.

•

DMA: Access to all zones except the PPB memory space

NOTE

The PPB space is dedicated only to the Cortex-M4 Private Peripheral Bus.

6.6.1

Master and Slave Access Priority Settings

Table 6-38 lists all the available masters (rows) and their access permissions to slaves (columns). If

multiple masters can access one slave, the table lists access priorities if arbitration is required. A lower

number in the table indicates a higher arbitration priority (the priority is always fixed).

(1)

Access from the DCODE to flash memory may be restricted if the device is operating in a secure

mode

(2)

Access from DMA to flash memory is restricted to Bank 1 if the device is operating in a secure mode

with IP protection enabled. In such cases, access to Bank 0 returns an error response

(3)

Although the SRAM is mapped to both Code and System spaces, accesses from DMA to SRAM must

use the System space addressing only.

Table 6-38. Master and Slave Access Priority

FLASH MEMORY

ROM

SRAM

PERIPHERALS

ICODE

DCODE

2 (1)

SBUS

DMA

1 (2)

1 (3)

MSP432P411VIPZ bảng dữ liệu(PDF) 127 Page - Texas Instruments

MSP432P411VIPZ bảng dữ liệu(HTML) 127 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL