MSP432P411VIPZ datasheet(46/212 Pages) TI1

46 / 212 page

MSP432P4111, MSP432P4011, MSP432P411Y

MSP432P401Y, MSP432P411V, MSP432P401V

SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018

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Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V

Specifications

5.26 Timing and Switching Characteristics

5.26.1 Reset Timing

Table 5-1 lists the latencies to recover from different types of resets.

(1)

See Section 6.8.1 for details on the various classes of resets on the device

Table 5-1. Reset Recovery Latencies

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

(1)

PARAMETER

MIN

TYP

MAX

UNIT

tSOFT

Latency from release of soft reset to first CPU instruction fetch

MCLK

cycles

tHARD

Latency from release of hard reset to release of soft reset

MCLK

cycles

tPOR

Latency from release of device POR to release of hard reset

µs

tCOLDPWR, 100nF

Latency from a cold power-up condition to release of device POR, CVCORE = 100 nF

300

400

µs

tCOLDPWR, 4.7µF

Latency from a cold power-up condition to release of device POR, CVCORE = 4.7 µF

400

500

µs

Table 5-2 lists the latencies to recover from an external reset applied on RSTn pin.

(1)

External reset is applied on RSTn pin, and the latency is measured from release of external reset to start of user application code.

Table 5-2. External Reset Recovery Latencies(1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

tAM_RSTn

External reset applied when device is in LDO-based or DC/DC-based active

modes,

MCLK = 1 to 48 MHz

4.5

tAMLF_RSTn, 128 kHz

External reset applied when device is in low-frequency active modes,

MCLK = 128 kHz

tAMLF_RSTn, 32 kHz

External reset applied when device is in low-frequency active modes,

MCLK = 32.768 kHz

tLPM0_RSTn

External reset applied when device is in LDO-based or DC/DC-based LPM0

modes,

MCLK = 1 to 48 MHz

4.5

tLPM0LF_RSTn, 128 kHz

External reset applied when device is in low-frequency LPM0 modes,

MCLK = 128 kHz

tLPM0LF_RSTn, 32 kHz

External reset applied when device is in low-frequency LPM0 modes,

MCLK = 32.768 kHz

tLPM3_LPM4_RSTn

External reset applied when device is in LPM3 or LPM4 modes,

MCLK = 24 or 48 MHz while entering LPM3 or LPM4 modes

4.5

tLPMx.5_RSTn

External reset applied when device is in LPM3.5 or LPM4.5 modes

4.5

5.26.2 Peripheral Register Access Timing

Table 5-3 lists the latency involved when CPU performs read or write access to peripheral registers.

(1)

The bridge that connects CPU to peripherals runs at half of the speed of the CPU.

(2)

The maximum value depends on the previous opcode executing in the CPU pipeline and the status of the bus (idle or busy performing

data access).

Table 5-3. Peripheral Register Access Latency

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

MIN

MAX

UNIT

treg_access

Number of CPU clock cycles required for read or write access to peripheral registers

2(1)

5(2)

MCLK

cycles

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