MSP432P411VIPZ datasheet(90/212 Pages) TI1

90 / 212 page

MSP432P4111, MSP432P4011, MSP432P411Y

MSP432P401Y, MSP432P411V, MSP432P401V

SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018

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Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V

Specifications

Table 5-43 lists the characteristics of the eUSCI in SPI slave mode.

(1)

fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI))

For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.

(2)

Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams

in Figure 5-71 and Figure 5-72.

(3)

Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-71

and Figure 5-72.

Table 5-43. eUSCI (SPI Slave Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

(see Note

(1))

PARAMETER

TEST CONDITIONS

VCC

MIN

MAX

UNIT

tSTE,LEAD

STE lead time, STE active to clock

1.62 V

3.7 V

tSTE,LAG

STE lag time, Last clock to STE inactive

1.62 V

3.7 V

tSTE,ACC

STE access time, STE active to SOMI data out

1.62 V

3.7 V

tSTE,DIS

STE disable time, STE inactive to SOMI high

impedance

1.62 V

3.7 V

tSU,SI

SIMO input data setup time

1.62 V

3.7 V

tHD,SI

SIMO input data hold time

1.62 V

3.7 V

tVALID,SO

SOMI output data valid time(2)

UCLK edge to SOMI valid,

CL = 20 pF

1.62 V

3.7 V

tHD,SO

SOMI output data hold time(3)

CL = 20 pF

1.62 V

3.7 V

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