MSP432P411VIPZ datasheet(88/212 Pages) TI1

88 / 212 page

MSP432P4111, MSP432P4011, MSP432P411Y

MSP432P401Y, MSP432P411V, MSP432P401V

SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018

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Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V

Specifications

Table 5-42 lists the characteristics of the eUSCI in SPI master mode.

(1)

fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave))

For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.

(2)

Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams

in Figure 5-69 and Figure 5-70.

(3)

Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data

on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 5-

69 and Figure 5-70.

Table 5-42. eUSCI (SPI Master Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

(1)

PARAMETER

TEST CONDITIONS

VCORE

VCC

MIN

MAX

UNIT

tSTE,LEAD

STE lead time, STE active to clock

UCSTEM = 1,

UCMODEx = 01 or 10

UCxCLK

cycles

tSTE,LAG

STE lag time, Last clock to STE inactive

UCSTEM = 1,

UCMODEx = 01 or 10

tSTE,ACC

STE access time, STE active to SIMO

data out

UCSTEM = 0,

UCMODEx = 01 or 10

1.62 V

3.7 V

tSTE,DIS

STE disable time, STE inactive to SIMO

high impedance

UCSTEM = 0,

UCMODEx = 01 or 10

1.62 V

3.7 V

tSU,MI

SOMI input data setup time

1.2 V

1.62 V

1.4 V

3.7 V

tHD,MI

SOMI input data hold time

1.62 V

3.7 V

tVALID,MO

SIMO output data valid time(2)

UCLK edge to SIMO valid,

CL = 20 pF

1.62 V

3.7 V

tHD,MO

SIMO output data hold time(3)

CL = 20 pF

1.62 V

3.7 V

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