MSP432P411VIPZ datasheet(98/212 Pages) TI1

98 / 212 page

Code

SRAM

Peripherals

Unused

Debug/Trace

Peripherals

0x0000_0000

0x1FFF_FFFF

0x3FFF_FFFF

0x5FFF_FFFF

0x7FFF_FFFF

0x9FFF_FFFF

0xBFFF_FFFF

0xDFFF_FFFF

0xFFFF_FFFF

0x2000_0000

0x4000_0000

0x6000_0000

0x8000_0000

0xA000_0000

0xC000_0000

0xE000_0000

MSP432P4111, MSP432P4011, MSP432P411Y

MSP432P401Y, MSP432P411V, MSP432P401V

SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018

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Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V

Detailed Description

For system trace, the processor integrates an Instrumentation Trace Macrocell (ITM) alongside data

watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system trace events, a

Serial Wire Viewer (SWV) can export a stream of software-generated messages, data trace, and profiling

information through a single pin.

NOTE

For detailed specifications and information on the programmer's model for the Cortex-M4

CPU and the associated peripherals mentioned throughout Section 6.2, see the appropriate

reference manual at www.arm.com.

6.3

Memory Map

The device supports a 4-GB address space that is divided into eight 512-MB zones (see Figure 6-1).

Figure 6-1. Device Memory Zones

6.3.1

Code Zone Memory Map

The region from 0x0000_0000 to 0x1FFF_FFFF is defined as the Code zone, and is accessible through

the ICODE and DCODE buses of the Cortex-M4 processor and through the system DMA. This region

maps the flash, the ROM, and the internal SRAM (permitting optimal single-cycle execution from the

SRAM).

Figure 6-2 shows MSP432P4x1xI-specific memory map of the Code zone, as visible to the user code.

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