MSP432P411VIPZ datasheet(128/212 Pages) TI1

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128

MSP432P4111, MSP432P4011, MSP432P411Y

MSP432P401Y, MSP432P411V, MSP432P401V

SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018

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Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V

Detailed Description

(1)

A reserved memory region returns 0h on reads and instruction fetches. Writes to this region are ignored.

(2)

If the user memory address is part of a secure region, this access returns an error if it is initiated by an unauthorized source. For more

details, see the device security application note.

(3)

Writes to this address are ignored if the sector has write protection enabled.

(4)

Reads from the bit-band region return 00h if the bit is clear and 01h if the bit is set.

(5)

See the Cortex-M4 technical reference manual at www.arm.com for details of the memory map of the internal PPB.

6.6.2

Memory Map Access Response

Table 6-39 summarizes the access responses to the entire memory map of MSP432P4x1x devices.

Table 6-39. Memory Map Access Response

ADDRESS RANGE

DESCRIPTION

READ (1)

WRITE (1)

INSTRUCTION

FETCH (1)

0x0000_0000 to 0x001F_FFFF

Flash Main Memory

OK (2), (3)

0x0020_0000 to 0x0020_7FFF

Flash Information Memory

OK (3)

0x0020_8000 to 0x00FF_FFFF

Reserved

Error

0x0100_0000 to 0x0103_FFFF

SRAM

0x0104_0000 to 0x01FF_FFFF

Reserved

Error

0x0200_0000 to 0x0200_07FF

ROM (Reserved)

Error

0x0200_0800 to 0x0200_7FFF

ROM

Error

0x0200_8000 to 0x1FFF_FFFF

Reserved

Error

0x2000_0000 to 0x2003_FFFF

SRAM

0x2004_0000 to 0x21FF_FFFF

Reserved

Error

0x2200_0000 to 0x23FF_FFFF

SRAM bit-band alias

OK (4)

Error

0x2400_0000 to 0x3FFF_FFFF

Reserved

Error

0x4000_0000 to 0x4001_FFFF

Peripheral

Error

0x4002_0000 to 0x41FF_FFFF

Reserved

Error

0x4200_0000 to 0x43FF_FFFF

Peripheral bit-band alias

OK (4)

Error

0x4400_0000 to 0xDFFF_FFFF

Reserved

Error

0xE000_0000 to 0xE003_FFFF

Internal PPB (5)

Error

0xE004_0000 to 0xE004_0FFF

TPIU (External PPB)

Error

0xE004_1000 to 0xE004_1FFF

Reserved

Error

0xE004_2000 to 0xE004_23FF

Reset Controller (External

PPB)

Error

0xE004_2400 to 0xE004_2FFF

Reserved

Error

0xE004_3000 to 0xE004_33FF

SYSCTL_A (External PPB)

Error

0xE004_3400 to 0xE004_3FFF

Reserved

Error

0xE004_4000 to 0xE004_43FF

SYSCTL_A (External PPB)

Error

0xE004_4400 to 0xE00F_EFFF

Reserved

Error

0xE00F_F000 to 0xE00F_FFFF

ROM Table (External PPB)

Error

0xE010_0000 to 0xFFFF_FFFF

Reserved

Error

6.7

Interrupts

The Cortex-M4 processor on MSP432P4x1x devices implements an NVIC with 64 external interrupt lines

and 8 levels of priority. From an application perspective, the interrupt sources at the device level are

divided into two classes, the NMI and the User Interrupts. Internally, the CPU exception model handles the

various exceptions (internal and external events including CPU instruction, memory, and bus fault

conditions) in a fixed and configurable order of priority. For details on the handling of various exception

priorities (including CPU reset and fault models), see the Arm-V7M architecture reference manual at

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