MSP432P411VIPZ datasheet(130/212 Pages) TI1

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MSP432P4111, MSP432P4011, MSP432P411Y

MSP432P401Y, MSP432P411V, MSP432P401V

SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018

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Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V

Detailed Description

Table 6-40. NVIC Interrupts (continued)

NVIC INTERRUPT INPUT

SOURCE

FLAGS IN SOURCE

(3)

DMA_INT0 has a different functionality from DMA_INT1, DMA_INT2, or DMA_INT3. See Section 6.5.2 for more details.

INTISR[28]

AES256

AESRDYIFG

INTISR[29]

RTC_C

OFIFG, RDYIFG, TEVIFG, AIFG, RT0PSIFG, RT1PSIFG

INTISR[30]

DMA_ERR

DMA error interrupt

INTISR[31]

DMA_INT3

DMA completion interrupt 3

INTISR[32]

DMA_INT2

DMA completion interrupt 2

INTISR[33]

DMA_INT1

DMA completion interrupt 1

INTISR[34]

DMA_INT0 (3)

DMA completion interrupt 0

INTISR[35]

I/O Port P1

P1IFG.x (x = 0 to 7)

INTISR[36]

I/O Port P2

P2IFG.x (x = 0 to 7)

INTISR[37]

I/O Port P3

P3IFG.x (x = 0 to 7)

INTISR[38]

I/O Port P4

P4IFG.x (x = 0 to 7)

INTISR[39]

I/O Port P5

P5IFG.x (x = 0 to 7)

INTISR[40]

I/O Port P6

P6IFG.x (x = 0 to 7)

INTISR[41]

LCD_F

LCD interrupt flags

INTISR[42]

Reserved

INTISR[43]

Reserved

INTISR[44]

Reserved

INTISR[45]

Reserved

INTISR[46]

Reserved

INTISR[47]

Reserved

INTISR[48]

Reserved

INTISR[49]

Reserved

INTISR[50]

Reserved

INTISR[51]

Reserved

INTISR[52]

Reserved

INTISR[53]

Reserved

INTISR[54]

Reserved

INTISR[55]

Reserved

INTISR[56]

Reserved

INTISR[57]

Reserved

INTISR[58]

Reserved

INTISR[59]

Reserved

INTISR[60]

Reserved

INTISR[61]

Reserved

INTISR[62]

Reserved

INTISR[63]

Reserved

NOTE

The Interrupt Service Routine (ISR) must ensure that the relevant interrupt flag in the source

peripheral is cleared before returning from the ISR. If this is not done, the same interrupt

may be incorrectly triggered again as a new event, even though the event has already been

processed by the ISR. As there may be a few cycles of delay between the execution of the

write command and the actual write reflecting in the interrupt flag register of the peripheral,

TI recommends performing the write and waiting for a few cycles before exiting the ISR.

Alternatively, the application can read the flag to ensure that it is cleared before exiting the

ISR.

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