MSP432P411VIPZ datasheet(129/212 Pages) TI1

129 / 212 page

129

MSP432P4111, MSP432P4011, MSP432P411Y

MSP432P401Y, MSP432P411V, MSP432P401V

www.ti.com

SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018

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Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V

Detailed Description

(1)

This source can also be mapped to the system NMI. See the MSP432P4xx SimpleLink™ Microcontrollers Technical Reference Manual

for more details.

(2)

The FPU of the Cortex-M4 can generate interrupts due to multiple floating-point exceptions. It is the responsibility of software to process

and clear the interrupt flags in the FPSCR.

6.7.1

NMI

The NMI input of the NVIC has the following possible sources:

•

External NMI pin (if configured in NMI mode)

•

Oscillator fault condition

•

Power Supply System (PSS) generated interrupts

•

Power Control Manager (PCM) generated interrupts

6.7.2

Device-Level User Interrupts

Table 6-40 lists the various interrupt sources and their connection to the NVIC inputs.

NOTE

Some sources may have multiple interrupt conditions, in which case the appropriate interrupt

status/flag register of the source must be examined to differentiate between the generating

conditions.

Table 6-40. NVIC Interrupts

NVIC INTERRUPT INPUT

SOURCE

FLAGS IN SOURCE

INTISR[0]

PSS (1)

INTISR[1]

CS (1)

INTISR[2]

PCM (1)

INTISR[3]

WDT_A

INTISR[4]

FPU_INT (2)

Combined interrupt from flags in the FPSCR (part of Cortex-M4 FPU)

INTISR[5]

FLCTL_A

FLCTL_A interrupt flags

INTISR[6]

COMP_E0

Comparator_E0 interrupt flags

INTISR[7]

COMP_E1

Comparator_E1 interrupt flags

INTISR[8]

Timer_A0

TA0CCTL0.CCIFG

INTISR[9]

Timer_A0

TA0CCTLx.CCIFG (x = 1 to 4), TA0CTL.TAIFG

INTISR[10]

Timer_A1

TA1CCTL0.CCIFG

INTISR[11]

Timer_A1

TA1CCTLx.CCIFG (x = 1 to 4), TA1CTL.TAIFG

INTISR[12]

Timer_A2

TA2CCTL0.CCIFG

INTISR[13]

Timer_A2

TA2CCTLx.CCIFG (x = 1 to 4), TA2CTL.TAIFG

INTISR[14]

Timer_A3

TA3CCTL0.CCIFG

INTISR[15]

Timer_A3

TA3CCTLx.CCIFG (x = 1 to 4), TA3CTL.TAIFG

INTISR[16]

eUSCI_A0

UART or SPI mode TX, RX, and status flags

INTISR[17]

eUSCI_A1

UART or SPI mode TX, RX, and status flags

INTISR[18]

eUSCI_A2

UART or SPI mode TX, RX, and status flags

INTISR[19]

eUSCI_A3

UART or SPI mode TX, RX, and status flags

INTISR[20]

eUSCI_B0

SPI or I2C mode TX, RX, and status flags (I2C in multiple-slave mode)

INTISR[21]

eUSCI_B1

SPI or I2C mode TX, RX, and status flags (I2C in multiple-slave mode)

INTISR[22]

eUSCI_B2

SPI or I2C mode TX, RX, and status flags (I2C in multiple-slave mode)

INTISR[23]

eUSCI_B3

SPI or I2C mode TX, RX, and status flags (I2C in multiple-slave mode)

INTISR[24]

Precision ADC

IFG[0-31], LOIFG, INIFG, HIIFG, RDYIFG, OVIFG, TOVIFG

INTISR[25]

Timer32_INT1

Timer32 interrupt for Timer 1

INTISR[26]

Timer32_INT2

Timer32 interrupt for Timer 2

INTISR[27]

Timer32_INTC

Timer32 combined interrupt

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