MSP432P411VIPZ datasheet(126/212 Pages) TI1

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126

MSP432P4111, MSP432P4011, MSP432P411Y

MSP432P401Y, MSP432P411V, MSP432P401V

SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018

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Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V

Detailed Description

NOTE

The entire ROM region returns an error response for write accesses. The lower 2KB of the

ROM always returns an error response for any access.

6.5

DMA

MSP432P4x1x devices implement an 8-channel Arm µDMA. This allows eight simultaneously active

channels for data transfer between memory and peripherals without needing to use the bandwidth of the

CPU (thereby reducing power by idling the CPU when there is no data processing required). In addition,

the DMA remains active in multiple low-power modes of operation, allowing for a very low power state in

which data can be transferred at low rates.

For maximum flexibility, up to eight DMA event sources can map to any of the eight channels. This is

controlled through configuration registers in the DMA. In addition, the DMA can generate up to four

interrupt requests (described in Section 6.5.2). For details regarding configuration of the DMA, see the

DMA chapter in the MSP432P4xx SimpleLink™ Microcontrollers Technical Reference Manual.

6.5.1

DMA Source Mapping

Each channel of the eight available channels has a control register that can select any of the device-level

DMA sources as the final source for that corresponding channel. Table 6-37 lists the sources available for

mapping to each channel, based on the value of the Source Config Register (SRCCFG).

Table 6-37. DMA Sources

CHANNEL

SRCCFG

Reserved

eUSCI_A0 TX

eUSCI_B0 TX0

eUSCI_B3 TX1

eUSCI_B2 TX2

eUSCI_B1 TX3

TA0CCR0

AES256_Trigger0

Reserved

eUSCI_A0 RX

eUSCI_B0 RX0

eUSCI_B3 RX1

eUSCI_B2 RX2

eUSCI_B1 RX3

TA0CCR2

AES256_Trigger1

Reserved

eUSCI_A1 TX

eUSCI_B1 TX0

eUSCI_B0 TX1

eUSCI_B3 TX2

eUSCI_B2 TX3

TA1CCR0

AES256_Trigger2

Reserved

eUSCI_A1 RX

eUSCI_B1 RX0

eUSCI_B0 RX1

eUSCI_B3 RX2

eUSCI_B2 RX3

TA1CCR2

Reserved

eUSCI_A2 TX

eUSCI_B2 TX0

eUSCI_B1 TX1

eUSCI_B0 TX2

eUSCI_B3 TX3

TA2CCR0

Reserved

eUSCI_A2 RX

eUSCI_B2 RX0

eUSCI_B1 RX1

eUSCI_B0 RX2

eUSCI_B3 RX3

TA2CCR2

Reserved

eUSCI_A3 TX

eUSCI_B3 TX0

eUSCI_B2 TX1

eUSCI_B1 TX2

eUSCI_B0 TX3

TA3CCR0

DMAE0

(External Pin)

Reserved

eUSCI_A3 RX

eUSCI_B3 RX0

eUSCI_B2 RX1

eUSCI_B1 RX2

eUSCI_B0 RX3

TA3CCR2

Precision ADC

NOTE

Any source marked as Reserved is unused. It may be used for software-controlled DMA

tasks, but typically it is reserved for enhancement purposes on future devices.

6.5.2

DMA Completion Interrupts

In the case of the Arm µDMA controller, it is usually the responsibility of software to maintain a list of

channels that have completed their operation. To provide further flexibility, MSP432P4x1x DMA supports

four DMA completion interrupts, which are mapped in the following way:

•

DMA_INT0: Logical OR of all completion events except those that are already mapped to DMA_INT1,

DMA_INT2, or DMA_INT3.

•

DMA_INT1, DMA_INT2, DMA_INT3: Can be mapped to the DMA completion event of any of the eight

channels.

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