MSP432P411VIPZ datasheet(125/212 Pages) TI1

125 / 212 page

BNK0_EN = 1

BNK1_EN = 0

BNK2_EN = 0

BNK3_EN = 0

BNK0_EN = 1

BNK1_EN = 1

BNK2_EN = 0

BNK3_EN = 0

BNK0_EN = 1

BNK1_EN = 1

BNK2_EN = 1

BNK3_EN = 0

BNK0_EN = 1

BNK1_EN = 1

BNK2_EN = 1

BNK3_EN = 1

Valid SRAM bank enables for SRAM with 4 banks

Conversion of invalid bank enables to valid setting

BNK0_EN = 1

BNK1_EN = 0

BNK2_EN = 1

BNK3_EN = 0

BNK0_EN = 1

BNK1_EN = 1

BNK2_EN = 1

BNK3_EN = 0

Invalid BNKx_EN setting

Valid BNKx_EN setting

125

MSP432P4111, MSP432P4011, MSP432P411Y

MSP432P401Y, MSP432P411V, MSP432P401V

www.ti.com

SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018

Submit Documentation Feedback

Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V

Detailed Description

Figure 6-7. Configuring SRAM Bank Enables

Bank 0 of SRAM is always enabled and cannot be disabled. For all other banks, any enable or disable

change results in the BNKEN_RDY bit of the SYS_SRAM_STAT register being set to 0 until the

configuration change is effective. Any accesses to the SRAM is stalled during this time, and access

resumes only after the SRAM banks are ready for read or write operations. This is handled transparently

and does not require any code intervention. See SRAM characteristics in the electrical specification for the

SRAM bank enable or disable latency.

6.4.2.2

SRAM Block Retention Configuration and Backup Memory

The application can optimize the leakage power consumption of the SRAM in LPM3 and LPM4 modes of

operation. To enable this, each SRAM bank is further divided into 8-KB blocks that can be individually

configured for retention. Blocks that are enabled for retention retain their data through the LPM3 and

LPM4 modes. The application can also retain a subset of the blocks in the enabled banks.

For example, the application may need 128KB of SRAM for its processing needs (two banks are kept

enabled). However, of these two banks, only one 8-KB block can contain critical data that must be

retained in LPM3 or LPM4, while the rest are powered off completely to minimize power consumption.

Block 0 of SRAM Bank 0 is always retained and cannot be powered down. Therefore, it also operates as a

possible backup memory in the LPM3, LPM4, and LPM3.5 modes of operation.

6.4.3

Utility SRAM

MSP432P4x1x devices support an additional 2KB of utility SRAM space in the peripheral memory map

region. This space can be used by the application for storing any application related data (for example,

DMA descriptors).

6.4.4

ROM

MSP432P4x1x devices support 32KB of ROM, with the rest of the 1-MB region reserved (for future

upgrades). The lower 2KB of the ROM is reserved for TI internal purposes and accesses to this space

return an error response. The rest of the ROM is used for driver libraries.

MSP432P411VIPZ bảng dữ liệu(PDF) 125 Page - Texas Instruments

MSP432P411VIPZ bảng dữ liệu(HTML) 125 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL