MSP432P411VIPZ datasheet(123/212 Pages) TI1

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MSP432P4111, MSP432P4011, MSP432P411Y

MSP432P401Y, MSP432P411V, MSP432P401V

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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018

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Detailed Description

6.4.1.3

Flash Operation

The flash memory provides multiple read and program modes of operation that the application can deploy.

Up to 128 bits (memory word width) can be programmed (set from 1 to 0) in a single program operation.

Although the CPU data buses are 32 bits wide, the flash can buffer 128-bit write data before initiating flash

programming, thereby making it more seamless and power efficient for software to program large blocks

of data at a time. In addition, the flash memory also supports a burst write mode that takes less time when

compared to programming words individually. See Flash Memory for information on timing parameters.

The flash main and information memory regions offer write/erase protection control at a sector granularity

to enable software to optimize operations like mass erase while protecting certain regions of the flash. In

low-power modes of operation, the flash memory is disabled and put in a power-down state to minimize

leakage.

For details on the flash memory and its various modes of operation and configuration, see the Flash

Controller A (FLCTL_A) chapter in the MSP432P4xx SimpleLink™ Microcontrollers Technical Reference

Manual .

NOTE

Depending on the CPU (MCLK) frequency and the active mode in use, the flash may need to

be accessed with single/multiple wait states. Whenever there is a change required in the

operating frequency, the application must ensure that the flash access wait states are

configured correctly before the frequency change is effected. See the electrical specification

for details on flash wait state requirements.

6.4.2

SRAM

MSP432P4x1x devices support up to 256KB of SRAM, with the rest of the 1-MB SRAM region reserved.

The SRAM is aliased in both Code and SRAM zones. This enables fast, single cycle execution of code

from the SRAM, as the Cortex-M4 processor pipelines instruction fetches to memory zones other than the

Code space. As with the flash memory, the SRAM can be powered down or placed in a low-leakage

retention state in low-power modes of operation.

Figure 6-6 shows the memory map of SRAM on MSP432P4x1x devices.

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