MSP432P411VIPZ datasheet(134/212 Pages) TI1

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134

MSP432P4111, MSP432P4011, MSP432P411Y

MSP432P401Y, MSP432P411V, MSP432P401V

SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018

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Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V

Detailed Description

6.8.2.2

Supply Supervisor and Monitor for High Side (SVSMH)

The SVSMH supervises and monitors the VCC. SVSMH has a programmable threshold setting and can be

used by the application to generate a reset or an interrupt if the VCC dips below the desired threshold. In

supervisor mode, the SVSMH generates a device reset (POR class reset). In monitor mode, the SVSMH

generates an interrupt. The SVSMH can also be disabled if monitoring and supervision of the supply

voltage are not required (offers further power savings).

6.8.2.3

Core Voltage Regulator

MSP432P4x1x devices can be programmed to operate with either the LDO or the DC/DC as the voltage

regulator for the digital logic in the core domain of the device. The DC/DC offers significant boost in power

efficiency for high-current high-performance applications. The LDO is a highly efficient regulator that offers

power advantages at lower VCC ranges and in the ultra-low-power modes of operation.

The core operating voltage (output of the LDO or DC/DC) is automatically set by the device depending on

the selected operating mode of the device (see Table 6-43 for further details). The device offers seamless

switching between LDO and DC/DC operating modes and also implements a seamless DC/DC fail-safe

mechanism.

6.8.3

Power Control Manager (PCM)

The PCM controls the operating modes of the device and the switching between the modes. Mode

selection is controlled by the application, which can choose modes to meet its power and performance

requirements. Table 6-43 lists the operating modes of the device.

Table 6-43. MSP432P4x1x Operating Modes

OPERATING MODE

DESCRIPTION

AM_LDO_VCORE0

LDO-based active mode, medium performance, core voltage level 0

LPM0_LDO_VCORE0

Same as AM_LDO_VCORE0, except that CPU is off (no code execution)

AM_LDO_VCORE1

LDO-based active mode, maximum performance, core voltage level 1

LPM0_LDO_VCORE1

Same as AM_LDO_VCORE1, except that CPU is off (no code execution)

AM_DCDC_VCORE0

DC/DC-based active mode, medium performance, core voltage level 0

LPM0_DCDC_VCORE0

Same as AM_DCDC_VCORE0, except that CPU is off (no code execution)

AM_DCDC_VCORE1

DC/DC-based active mode, maximum performance, core voltage level 1

LPM0_DCDC_VCORE1

Same as AM_DCDC_VCORE1, except that CPU is off (no code execution)

AM_LF_VCORE0

LDO-based low-frequency active mode, core voltage level 0

LPM0_LF_VCORE0

Same as AM_LF_VCORE0, except that CPU is off (no code execution)

AM_LF_VCORE1

LDO-based low-frequency active mode, core voltage level 1

LPM0_LF_VCORE1

Same as AM_LF_VCORE1, except that CPU is off (no code execution)

LPM3_VCORE0

LDO-based low-power mode with full state retention, core voltage level 0. In addition to RTC_C and WDT_A,

other peripherals can be operational with an external or internal low-frequency clocks up to 128 kHz. See

Table 6-44 for peripherals that are available in this mode.

LPM3_VCORE1

LDO-based low-power mode with full state retention, core voltage level 1. In addition to RTC_C and WDT_A,

other peripherals can be operational with an external or internal low-frequency clocks up to 128 kHz. See

Table 6-44 for peripherals that are available in this mode.

LPM4_VCORE0

LDO-based low-power mode with full state retention, core voltage level 0.Peripherals can be operational out of

external clocks up to 128 kHz. See Table 6-44 for peripherals that are available in this mode.

LPM4_VCORE1

LDO-based low-power mode with full state retention, core voltage level 1.Peripherals can be operational out of

external clocks up to 128 kHz. See Table 6-44 for peripherals that are available in this mode.

LPM3.5

LDO-based low-power mode, core voltage level 0, no retention of peripheral registers, RTC_C and WDT_A can

be active

LPM4.5

Core voltage off, wakeup only through pin reset or wakeup-capable I/Os

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