MSP432P411VIPZ datasheet(138/212 Pages) TI1

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MSP432P4111, MSP432P4011, MSP432P411Y

MSP432P401Y, MSP432P411V, MSP432P401V

SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018

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Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V

Detailed Description

6.9.2.1

Port Mapping Definitions

The port mapping controller on MSP432P4x1x devices allows reconfigurable mapping of digital functions

on ports P2, P3, and P7.

Table 6-46. Port Mapping Mnemonics and Functions

VALUE

PxMAPy MNEMONIC

INPUT PIN FUNCTION

OUTPUT PIN FUNCTION

PM_NONE

None

DVSS

PM_UCA0CLK

eUSCI_A0 clock input/output (direction controlled by eUSCI)

PM_UCA0RXD

eUSCI_A0 UART RXD (direction controlled by eUSCI – input)

PM_UCA0SOMI

eUSCI_A0 SPI slave out master in (direction controlled by eUSCI)

PM_UCA0TXD

eUSCI_A0 UART TXD (direction controlled by eUSCI – output)

PM_UCA0SIMO

eUSCI_A0 SPI slave in master out (direction controlled by eUSCI)

PM_UCB0CLK

eUSCI_B0 clock input/output (direction controlled by eUSCI)

PM_UCB0SDA

eUSCI_B0 I2C data (open drain and direction controlled by eUSCI)

PM_UCB0SIMO

eUSCI_B0 SPI slave in master out (direction controlled by eUSCI)

PM_UCB0SCL

eUSCI_B0 I2C clock (open drain and direction controlled by eUSCI)

PM_UCB0SOMI

eUSCI_B0 SPI slave out master in (direction controlled by eUSCI)

PM_UCA1STE

eUSCI_A1 SPI slave transmit enable (direction controlled by eUSCI)

PM_UCA1CLK

eUSCI_A1 clock input/output (direction controlled by eUSCI)

PM_UCA1RXD

eUSCI_A1 UART RXD (direction controlled by eUSCI – input)

PM_UCA1SOMI

eUSCI_A1 SPI slave out master in (direction controlled by eUSCI)

PM_UCA1TXD

eUSCI_A1 UART TXD (direction controlled by eUSCI – output)

PM_UCA1SIMO

eUSCI_A1 SPI slave in master out (direction controlled by eUSCI)

PM_UCA2STE

eUSCI_A2 SPI slave transmit enable (direction controlled by eUSCI)

PM_UCA2CLK

eUSCI_A2 clock input/output (direction controlled by eUSCI)

PM_UCA2RXD

eUSCI_A2 UART RXD (direction controlled by eUSCI – input)

PM_UCA2SOMI

eUSCI_A2 SPI slave out master in (direction controlled by eUSCI)

PM_UCA2TXD

eUSCI_A2 UART TXD (direction controlled by eUSCI – output)

PM_ UCA2SIMO

eUSCI_A2 SPI slave in master out (direction controlled by eUSCI)

PM_UCB2STE

eUSCI_B2 SPI slave transmit enable (direction controlled by eUSCI)

PM_UCB2CLK

eUSCI_B2 clock input/output (direction controlled by eUSCI)

PM_UCB2SDA

eUSCI_B2 I2C data (open drain and direction controlled by eUSCI)

PM_UCB2SIMO

eUSCI_B2 SPI slave in master out (direction controlled by eUSCI)

PM_UCB2SCL

eUSCI_B2 I2C clock (open drain and direction controlled by eUSCI)

PM_UCB2SOMI

eUSCI_B2 SPI slave out master in (direction controlled by eUSCI)

PM_TA0CCR0A

TA0 CCR0 capture input CCI0A

TA0 CCR0 compare output Out0

PM_TA0CCR1A

TA0 CCR1 capture input CCI1A

TA0 CCR1 compare output Out1

PM_TA0CCR2A

TA0 CCR2 capture input CCI2A

TA0 CCR2 compare output Out2

PM_TA0CCR3A

TA0 CCR3 capture input CCI3A

TA0 CCR3 compare output Out3

PM_TA0CCR4A

TA0 CCR4 capture input CCI4A

TA0 CCR4 compare output Out4

PM_TA1CCR1A

TA1 CCR1 capture input CCI1A

TA1 CCR1 compare output Out1

PM_TA1CCR2A

TA1 CCR2 capture input CCI2A

TA1 CCR2 compare output Out2

PM_TA1CCR3A

TA1 CCR3 capture input CCI3A

TA1 CCR3 compare output Out3

PM_TA1CCR4A

TA1 CCR4 capture input CCI4A

TA1 CCR4 compare output Out4

PM_TA0CLK

Timer_A0 external clock input

None

PM_C0OUT

None

Comparator-E0 output

PM_TA1CLK

Timer_A1 external clock input

None

PM_C1OUT

None

Comparator-E1 output

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