MSP432P411VIPZ datasheet(139/212 Pages) TI1

139 / 212 page

139

MSP432P4111, MSP432P4011, MSP432P411Y

MSP432P401Y, MSP432P411V, MSP432P401V

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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018

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Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V

Detailed Description

Table 6-46. Port Mapping Mnemonics and Functions (continued)

VALUE

PxMAPy MNEMONIC

INPUT PIN FUNCTION

OUTPUT PIN FUNCTION

(1)

The value of the PM_ANALOG mnemonic is 31. The port mapping registers are 5 bits wide, and the upper bits are ignored, which

results in a read value of 31.

PM_DMAE0

DMAE0 input

None

PM_SMCLK

None

SMCLK

31 (0FFh) (1)

PM_ANALOG

Disables the output driver and the input Schmitt trigger to prevent parasitic cross currents

when applying analog signals.

(1)

Not available on the 64-pin RGC package.

Table 6-47. Default Mapping

PIN NAME

PxMAPy MNEMONIC

INPUT PIN FUNCTION

OUTPUT PIN FUNCTION

P2.0/PM_UCA1STE/L11

PM_UCA1STE

eUSCI_A1 SPI slave transmit enable (direction controlled by eUSCI)

P2.1/PM_UCA1CLK/L10

PM_UCA1CLK

eUSCI_A1 clock input/output (direction controlled by eUSCI)

P2.2/PM_UCA1RXD/

PM_UCA1SOMI/L9

PM_UCA1RXD/

PM_UCA1SOMI

eUSCI_A1 UART RXD (direction controlled by eUSCI – input)

eUSCI_A1 SPI slave out master in (direction controlled by eUSCI)

P2.3/PM_UCA1TXD/

PM_UCA1SIMO/L8

PM_UCA1TXD/

PM_UCA1SIMO

eUSCI_A1 UART TXD (direction controlled by eUSCI – output)/

eUSCI_A1 SPI slave in master out (direction controlled by eUSCI)

P2.4/PM_TA0.1/L23 (1)

PM_TA0CCR1A

TA0 CCR1 capture input CCI1A

TA0 CCR1 compare output Out1

P2.5/PM_TA0.2/L22 (1)

PM_TA0CCR2A

TA0 CCR2 capture input CCI2A

TA0 CCR2 compare output Out2

P2.6/PM_TA0.3/L21 (1)

PM_TA0CCR3A

TA0 CCR3 capture input CCI3A

TA0 CCR3 compare output Out3

P2.7/PM_TA0.4/L20 (1)

PM_TA0CCR4A

TA0 CCR4 capture input CCI4A

TA0 CCR4 compare output Out4

P3.0/PM_UCA2STE/L7

PM_UCA2STE

eUSCI_A2 SPI slave transmit enable (direction controlled by eUSCI)

P3.1/PM_UCA2CLK/L6

PM_UCA2CLK

eUSCI_A2 clock input/output (direction controlled by eUSCI)

P3.2/PM_UCA2RXD/

PM_UCA2SOMI/L5

PM_UCA2RXD/

PM_UCA2SOMI

eUSCI_A2 UART RXD (direction controlled by eUSCI – input)/

eUSCI_A2 SPI slave out master in (direction controlled by eUSCI)

P3.3/PM_UCA2TXD/

PM_UCA2SIMO/L4

PM_UCA2TXD/

PM_UCA2SIMO

eUSCI_A2 UART TXD (direction controlled by eUSCI – output)/

eUSCI_A2 SPI slave in master out (direction controlled by eUSCI)

P3.4/PM_UCB2STE/L3

PM_UCB2STE

eUSCI_B2 SPI slave transmit enable (direction controlled by eUSCI)

P3.5/PM_UCB2CLK/L2

PM_UCB2CLK

eUSCI_B2 clock input/output (direction controlled by eUSCI)

P3.6/PM_UCB2SIMO/

PM_UCB2SDA/L1

PM_UCB2SIMO/

PM_UCB2SDA

eUSCI_B2 SPI slave in master out (direction controlled by eUSCI)/

eUSCI_B2 I2C data (open drain and direction controlled by eUSCI)

P3.7/PM_UCB2SOMI/

PM_UCB2SCL/L0

PM_UCB2SOMI/

PM_UCB2SCL

eUSCI_B2 SPI slave out master in (direction controlled by eUSCI)/

eUSCI_B2 I2C clock (open drain and direction controlled by eUSCI)

P7.0/PM_SMCLK/

PM_DMAE0/R03

PM_SMCLK/

PM_DMAE0

DMAE0 input

SMCLK

P7.1/PM_C0OUT/

PM_TA0CLK/R13

PM_C0OUT/

PM_TA0CLK

Timer_A0 external clock input

Comparator-E0 output

P7.2/PM_C1OUT/

PM_TA1CLK/R23

PM_C1OUT/

PM_TA1CLK

Timer_A1 external clock input

Comparator-E1 output

P7.3/PM_TA0.0

PM_TA0CCR0A

TA0 CCR0 capture input CCI0A

TA0 CCR0 compare output Out0

P7.4/PM_TA1.4/C0.5/L31 (1)

PM_TA1CCR4A

TA1 CCR4 capture input CCI4A

TA1 CCR4 compare output Out4

P7.5/PM_TA1.3/C0.4/L30 (1)

PM_TA1CCR3A

TA1 CCR3 capture input CCI3A

TA1 CCR3 compare output Out3

P7.6/PM_TA1.2/C0.3/L29 (1)

PM_TA1CCR2A

TA1 CCR2 capture input CCI2A

TA1 CCR2 compare output Out2

P7.7/PM_TA1.1/C0.2/L28 (1)

PM_TA1CCR1A

TA1 CCR1 capture input CCI1A

TA1 CCR1 compare output Out1

6.9.3

Timer_A

Timers TA0, TA1, TA2, and TA3 are 16-bit timers and counters (Timer_A type) with five capture/compare

registers each. Each timer supports multiple captures and compares, PWM outputs, and interval timing.

Each has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow

conditions and from each capture/compare register.

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