MSP432P411VIPZ datasheet(137/212 Pages) TI1

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137

MSP432P4111, MSP432P4011, MSP432P411Y

MSP432P401Y, MSP432P411V, MSP432P401V

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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018

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Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V

Detailed Description

6.8.5

System Controller (SYSCTL_A)

The SYSCTL_A is a set of various miscellaneous features of the device, including device memory

configuration, RSTn/NMI function selection, clock run/stop control, watchdog configuration for selecting

reset classes and device NMI source configuration and status. In addition, the SYSCTL_A enables device

security features like JTAG and SWD lock and IP protection, which can be used to protect unauthorized

accesses either to the entire device memory map or to certain selected regions of the flash.

NOTE

Like with the Cortex-M4 system control registers (in the internal PPB space), the System

Controller module registers are mapped to the Cortex-M4 external PPB. This keeps the

System Controller module accessible even when hard or soft resets are active.

6.9

Peripherals

The following sections describe the peripherals that are available on the MSP432P4x1x devices. For

details on these peripherals, see the MSP432P4xx SimpleLink™ Microcontrollers Technical Reference

Manual.

6.9.1

Digital I/O

Up to 10 8-bit I/O ports are implemented.

•

All individual I/O bits are independently programmable.

•

Any combination of input, output, and interrupt conditions is possible.

•

Programmable pullup or pulldown on all ports

•

Edge-selectable interrupt capability is available on ports P1 to P6.

•

Wake-up capability from LPM3, LPM4, LPM3.5, and LPM4.5 modes on ports P1 to P6.

•

Read/write access to port-control registers is supported by all instructions.

•

Ports can be accessed byte-wise or in pairs (16-bit width).

•

Capacitive Touch functionality is supported on all pins of ports P1 to P10 and PJ.

•

Four 20-mA high-drive I/Os on pins P2.0 to P2.3

•

Glitch filtering capability on selected digital I/Os

6.9.1.1

Glitch Filtering on Digital I/Os

Some of the interrupt and wake-up capable digital I/Os can suppress glitches through the use of analog

glitch filter to prevent unintentional interrupt or wake-up during device operation. The analog filter

suppresses a minimum of 250-ns wide glitches. The glitch filter on these selected digital I/Os is enabled

by default. If the glitch filtering capability is not required in the application, it can be bypassed using the

SYS_DIO_GLTFLT_CTL register. When GLTFLT_EN bit in this register is cleared, the glitch filters on all

the digital I/Os are bypassed. The glitch filter is automatically bypassed on a digital I/O when it is

configured for peripheral or analog functionality by programming the respective PySEL0.x and PySEL1.x

registers.

NOTE

The glitch filter is implemented on the following digital I/Os on MSP432P4x1x devices: P1.0,

P1.4, P1.5, P3.0, P3.4, P3.5, P6.6, and P6.7.

6.9.2

Port Mapping Controller (PMAPCTL)

The port mapping controller allows flexible and reconfigurable mapping of digital functions.

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