CY7C65013
CY7C65113
Document #: 38-08002 Rev. *B
Page 33 of 51
An alternate means of forcing the downstream ports is through the Hub Ports Force Low Register (Figure 16-5) and Hub Ports
Force High Register (Figure 16-6). With these registers the pins of the downstream ports can be individually forced LOW, or left
unforced. Unlike the Hub Downstream Ports Control Register, above, the Force Low Register does not produce standard USB
edge rate control on the forced pins. However, this register allows downstream port pins to be held LOW in suspend. This register
can be used to drive SE0 on all downstream ports when unconfigured, as required in the USB 1.1 specification
.
The data state of downstream ports can be read through the HUB Ports SE0 Status Register (Figure 16-7) and the Hub Ports
Data Register (Figure 16-8). The data read from the Hub Ports Data Register is the differential data only and is independent of
the settings of the Hub Ports Speed Register (Figure 16-2). When the SE0 condition is sensed on a downstream port, the
corresponding bits of the Hub Ports Data Register hold the last differential data state before the SE0. Hub Ports SE0 Status
Register and Hub Ports Data Register are cleared upon reset or bus reset
.
Hub Downstream Ports Control Register
Address
0x4B
Bit #
7654321
0
Bit Name
Port 4
Control Bit 1
Port 4
Control Bit 0
Port 3
Control Bit 1
Port 3
Control Bit 0
Port 2
Control Bit 1
Port 2
Control Bit 0
Port 1
Control Bit 1
Port 1
Control Bit
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0000000
0
Figure 16-4. Hub Downstream Ports Control Register
Table 16-1. Control Bit Definition for Downstream Ports
Control Bits
Control Action
Bit1
Bit 0
0
0
Not Forcing (Normal USB Function)
0
1
Force Differential ‘1’ (D+ HIGH, D– LOW)
1
0
Force Differential ‘0’ (D+ LOW, D– HIGH)
1
1
Force SE0 state
Hub Ports Force Low
Address 0x51
Bit #
76543
2
1
0
Bit Name
Force Low
D+[4]
Force Low
D-[4]
Force Low
D+[3]
Force Low
D–[3]
Force Low
D+[2]
Force Low
D–[2]
Force Low
D+[1]
Force Low
D–[1]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
00000
0
0
0
Figure 16-5. Hub Ports Force Low Register
Hub Ports Force Low
Address 0x52
Bit #
7
6
543210
Bit Name
Reserved
Reserved
Force Low
D+[7]
Force Low
D–[7]
Force Low
D+[6]
Force Low
D–[6]
Force Low
D+[5]
Force Low
D–[5]
Read/Write
–
–
R/W
R/W
R/W
R/W
R/W
R/W
Reset
–
–
000000
Figure 16-6. Hub Ports Force Low Register
Hub Ports SE0 Status
Address 0x4F
Bit #
7
6
5432
10
Bit Name
Reserved
Port 7
SE0 Status
Port 6
SE0 Status
Port 5
SE0 Status
Port 4
SE0 Status
Port 3
SE0 Status
Port 2
SE0 Status
Port 1
SE0 Status
Read/Write
R
R
RRR
RRR
Reset
0
0
0000
00
Figure 16-7. Hub Ports SE0 Status Register
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