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CY7C65013
CY7C65113
Document #: 38-08002 Rev. *B
Page 18 of 51
9.0
General-purpose I/O Ports
There are up to 32 GPIO pins (P0[7:0], P1[7:4,2:0], P2[7:3], and P3[1:0]) for the hardware interface. The number of GPIO pins
depends on package type. See Section 3.0 for the port pins availability on different package types. Each port can be configured
as inputs with internal pull-ups, open drain outputs, or traditional CMOS outputs. Port 3 offers a higher current drive, with typical
current sink capability of 12 mA. The data for each GPIO port is accessible through the data registers. Port data registers are
shown in Figure 9-2 through Figure 9-5, and are set to 1 on reset
.
Figure 9-1. Block Diagram of a GPIO Pin
Port 0 Data
Address 0x00
Bit #
7654321
0
Bit Name
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
1111111
1
Figure 9-2. Port 0 Data
Port 1 Data
Address 0x01
Bit #
76543210
Bit Name
P1.7
P1.6
P1.5
P1.4
Reserved
P1.2
P1.1
P1.0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
11111111
Figure 9-3. Port1 Data
Port 2 Data
Address 0x02
Bit #
765
43
210
Bit Name
P2.7
P2.6
P2.5
P2.4
P2.3
Reserved
Reserved
Reserved
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
111
11
111
Figure 9-4. Port 2 Data
GPIO
VCC
14 k
Ω
GPIO
CFG
mode
2-bits
Data
Out
Latch
Internal
Data Bus
Port Read
Port Write
Interrupt
Enable
Interrupt
Controller
Q1
Q3*
Q2
*Port 0,1,2: Low Isink
Port 3: High Isink
Data
Interrupt
Latch
OE
Reg_Bit
STRB
Data
In
Latch
(Latch is Transparent)
PIN
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