9 / 51 page  CY7C65013 CY7C65113 Document #: 38-08002 Rev. *B Page 9 of 51 4.0 Product Summary Tables 4.1 Pin Assignments 3.0 Pin Configurations Table 4-1. Pin Assignments Name I/O 48-pin 28-pin Description D+[0], D–[0] I/O 7, 8 5, 6 Upstream port, USB differential data. D+[1], D–[1] I/O 10, 11 7, 8 Downstream Port 1, USB differential data. D+[2], D–[2] I/O 13, 14 9, 10 Downstream Port 2, USB differential data. D+[3], D–[3] I/O 41, 42 23, 24 Downstream Port 3, USB differential data. D+[4], D–[4] I/O 38, 39 21, 22 Downstream Port 4, USB differential data. D+[5], D–[5] I/O 35, 36 Downstream Port 5, USB differential data. D+[6], D–[6] I/O 31, 32 Downstream Port 6, USB differential data. D+[7], D–[7] I/O 18, 19 Downstream Port 7, USB differential data. P0 I/O P1[7:0] 21, 25, 22, 26, 23, 27, 24, 28 P1[7:0] 11, 15, 12, 16, 13, 17, 14, 18 GPIO Port 0 capable of sinking 7 mA (typical). P1 I/O P1[7:4,2:0] 5, 44, 4, 45; 46, 3, 47 P1[2:0] 25, 27, 26 GPIO Port 1 capable of sinking 7 mA (typical). P2 I/O P2[7:3] 20, 30, 17,33, 15 GPIO Port 2 capable of sinking 12 mA (typical). P3 I/O P3[1:0] 6, 43 GPIO Port 3, capable of sinking 12 mA (typical). XTALIN IN 2 2 6-MHz crystal or external clock input. 1 2 3 4 5 6 7 9 11 12 13 14 XTALIN 10 8 15 17 16 19 18 21 20 23 22 25 24 26 28 27 VCC P1[1] P1[0] P1[2] D–[3] D+[3] D–[4] D+[4] VREF GND D+[0] D–[0] D+[1] D–[1] D+[2] D–[2] P0[7] P0[5] P0[3] P0[1] XTALOUT GND VPP P0[0] P0[2] P0[4] P0[6] CY7C65113 28-pin SOIC CY7C65013 1 2 3 4 5 6 7 9 11 12 13 14 15 16 18 17 XTALIN 10 8 19 20 31 30 29 33 32 35 34 37 36 39 38 41 40 43 42 45 44 46 48 47 21 22 23 24 25 27 26 28 VCC P1[0] P1[2] P1[4] P1[6] P3[0] D–[3] D+[3] P1[1] P1[5] P1[7] P3[1] D+[0] D–[0] GND D+[1] D–[1] VREF D+[2] D–[2] P2[3] GND P2[5] D+[7] D–[7] P2[7] P0[7] P0[5] P0[3] P0[1] XTALOUT GND D–[4] D+[4] VREF D–[5] D+[5] GND P2[4] D–[6] D+[6] P2[6] VPP P0[0] P0[2] P0[4] P0[6] 48-pin SSOP Top View |
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