CY7C65013
CY7C65113
Document #: 38-08002 Rev. *B
Page 28 of 51
14.2
Interrupt Latency
Interrupt latency can be calculated from the following equation:
For example, if a 5-clock cycle instruction such as JC is being executed when an interrupt occurs, the first instruction of the
Interrupt Service Routine executes a minimum of 16 clocks (1+10+5) or a maximum of 20 clocks (5+10+5) after the interrupt is
issued. For a 12-MHz internal clock (6-MHz crystal), 20 clock periods is 20/12 MHz = 1.667
µs.
14.3
USB Bus Reset Interrupt
The USB Controller recognizes a USB Reset when a Single Ended Zero (SE0) condition persists on the upstream USB port for
12–16
µs. SE0 is defined as the condition in which both the D+ line and the D– line are LOW. A USB Bus Reset may be recognized
for an SE0 as short as 12
µs, but is always recognized for an SE0 longer than 16 µs. When a USB Bus Reset is detected, bit 5
of the Processor Status and Control Register (Figure 13-1) is set to record this event. In addition, the controller clears the following
registers:
SIE Section: .... USB Device Address Registers (0x10, 0x40)
Hub Section: ......................Hub Ports Connect Status (0x48)
........................................................ Hub Ports Enable (0x49)
........................................................ Hub Ports Speed (0x4A)
.................................................... Hub Ports Suspend (0x4D)
.......................................... Hub Ports Resume Status (0x4E)
................................................. Hub Ports SE0 Status (0x4F)
........................................................... Hub Ports Data (0x50)
............................................. Hub Downstream Force (0x51).
A USB Bus Reset Interrupt is generated at the end of the USB Bus Reset condition when the SE0 state is deasserted. If the USB
reset occurs during the start-up delay following a POR, the delay is aborted as described in Section 7.1.
14.4
Timer Interrupt
There are two periodic timer interrupts: the 128-
µs interrupt and the 1.024-ms interrupt. The user should disable both timer
interrupts before going into the suspend mode to avoid possible conflicts between servicing the timer interrupts first or the suspend
request first.
14.5
USB Endpoint Interrupts
There are five USB endpoint interrupts, one per endpoint. A USB endpoint interrupt is generated after the USB host writes to a
USB endpoint FIFO or after the USB controller sends a packet to the USB host. The interrupt is generated on the last packet of
the transaction (e.g., on the host’s ACK on an IN transfer, or on the device ACK on an OUT transfer). If no ACK is received during
an IN transaction, no interrupt is generated.
14.6
USB Hub Interrupt
A USB hub interrupt is generated by the hardware after a connect/disconnect change, babble, or a resume event is detected by
the USB repeater hardware. The babble and resume events are additionally gated by the corresponding bits of the Hub Port
Enable Register (Figure 16-3). The connect/disconnect event on a port does not generate an interrupt if the SIE does not drive
the port (i.e., the port is being forced).
14.7
GPIO Interrupt
Each of the GPIO pins can generate an interrupt, if enabled. The interrupt polarity can be programmed for each GPIO port as
part of the GPIO configuration. All of the GPIO pins share a single interrupt vector, which means the firmware needs to read
theGPIO ports with enabled interrupts to determine which pin or pins caused an interrupt. A block diagram of the GPIO interrupt
logic is shown in Figure 14-4
Interrupt latency = (Number of clock cycles remaining in the current instruction) +
(10 clock cycles for the CALL instruction) +
(5 clock cycles for the JMP instruction)
Vietnamese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
