CY7C65013
CY7C65113
Document #: 38-08002 Rev. *B
Page 4 of 51
LIST OF FIGURES
Figure 5-1. Program Memory Space with Interrupt Vector Table ........................................................ 13
Figure 6-1. Clock Oscillator On-Chip Circuit ........................................................................................ 16
Figure 7-1. Watchdog Reset (Address 0x26) ...................................................................................... 17
Figure 9-1. Block Diagram of a GPIO Pin ............................................................................................ 18
Figure 9-2. Port 0 Data ........................................................................................................................ 18
Figure 9-3. Port1 Data ......................................................................................................................... 18
Figure 9-4. Port 2 Data ........................................................................................................................ 18
Figure 9-6. GPIO Configuration Register ............................................................................................. 19
Figure 9-5. Port 3 Data ........................................................................................................................ 19
Figure 9-7. Port 0 Interrupt Enable ...................................................................................................... 20
Figure 9-8. Port 1 Interrupt Enable ...................................................................................................... 20
Figure 10-1. Timer LSB Register ......................................................................................................... 21
Figure 10-2. Timer MSB Register ........................................................................................................ 21
Figure 9-9. Port 2 Interrupt Enable ...................................................................................................... 21
Figure 9-10. Port 3 Interrupt Enable .................................................................................................... 21
Figure 10-3. Timer Block Diagram ....................................................................................................... 22
Figure 11-1. I2C Configuration Register ............................................................................................... 22
Figure 12-1. I2C Data Register ............................................................................................................. 23
Figure 12-2. I2C Status and Control Register ...................................................................................... 23
Figure 13-1. Processor Status and Control Register ........................................................................... 24
Figure 14-1. Global Interrupt Enable Register ..................................................................................... 25
Figure 14-2. USB Endpoint Interrupt Enable Register ......................................................................... 26
Figure 14-3. Interrupt Controller Function Diagram ............................................................................. 27
Figure 14-4. GPIO Interrupt Structure ................................................................................................. 29
Figure 16-1. Hub Ports Connect Status ............................................................................................... 31
Figure 16-2. Hub Ports Speed ............................................................................................................. 31
Figure 16-3. Hub Ports Enable Register .............................................................................................. 32
Figure 16-4. Hub Downstream Ports Control Register ........................................................................ 33
Figure 16-5. Hub Ports Force Low Register ........................................................................................ 33
Figure 16-6. Hub Ports Force Low Register ........................................................................................ 33
Figure 16-7. Hub Ports SE0 Status Register ....................................................................................... 33
Figure 16-8. Hub Ports Data Register ................................................................................................. 34
Figure 16-9. Hub Ports Suspend Register ........................................................................................... 34
Figure 16-10. Hub Ports Resume Status Register .............................................................................. 35
Figure 16-11. USB Status and Control Register .................................................................................. 35
Figure 17-1. USB Device Address Registers ....................................................................................... 36
Figure 17-2. USB Device Endpoint Zero Mode Registers ................................................................... 37
Figure 17-3. USB Non-control Device Endpoint Mode Registers ........................................................ 38
Figure 17-4. USB Endpoint Counter Registers .................................................................................... 39
Figure 17-5. Token/Data Packet Flow Diagram ...................................................................................40
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