CY7C65013-PVC datasheet(27/51 Pages) CYPRESS

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CY7C65013

CY7C65113

Document #: 38-08002 Rev. *B

Page 27 of 51

The DI and EI instructions can be used to disable and enable interrupts, respectively. These instructions affect only the Global

Interrupt Enable bit of the CPU. If desired, EI can be used to re-enable interrupts while inside an ISR, instead of waiting for the

RETI that exits the ISR. While the global interrupt enable bit is cleared, the presence of a pending interrupt can be detected by

examining the IRQ Sense bit (Bit 7 in the Processor Status and Control Register).

14.1

Interrupt Vectors

The Interrupt Vectors supported by the USB Controller are listed in Table 14-1. The lowest-numbered interrupt (USB Bus Reset

interrupt) has the highest priority, and the highest-numbered interrupt (I2C interrupt) has the lowest priority.

Although Reset is not an interrupt, the first instruction executed after a reset is at PROM address 0x0000h—which corresponds

to the first entry in the Interrupt Vector Table. Because the JMP instruction is two bytes long, the interrupt vectors occupy two bytes.

Table 14-1. Interrupt Vector Assignments

Interrupt Vector Number

ROM Address

Function

Not Applicable

0x0000

Execution after Reset begins here

0x0002

USB Bus Reset interrupt

0x0004

128-

µs timer interrupt

0x0006

1.024-ms timer interrupt

0x0008

USB Address A Endpoint 0 interrupt

0x000A

USB Address A Endpoint 1 interrupt

0x000C

USB Address A Endpoint 2 interrupt

0x000E

USB Address B Endpoint 0 interrupt

0x0010

USB Address B Endpoint 1 interrupt

0x0012

USB Hub interrupt

0x0014

DAC interrupt

0x0016

GPIO interrupt

0x0018

I2C interrupt

CLR

Global

Interrupt

Acknowledge

IRQout

USB Reset Clear Interrupt

Interrupt Priority Encoder

Enable [0]

Enable

Bit

CLR

USB Reset IRQ

128-

µs CLR

128-

µs IRQ

1-ms CLR

1-ms IRQ

AddrA EP0 IRQ

AddrA EP0 CLR

I2C IRQ

Vector

Enable [6]

CLK

CLR

CLK

I2C CLR

I2C Int

USB Reset Int

AddrA EP1 IRQ

AddrA EP1 CLR

IRQ Sense

IRQ

Controlled by DI, EI, and

RETI Instructions

DAC IRQ

DAC CLR

To CPU

CPU

GPIO IRQ

GPIO CLR

Hub IRQ

Hub CLR

AddrA EP2 IRQ

AddrA EP2 CLR

AddrB EP0 IRQ

AddrB EP0 CLR

AddrB EP1 IRQ

AddrB EP1 CLR

(Reg 0x20)

CLR

Enable [2]

CLK

AddrA ENP2 Int

(Reg 0x21)

Int Enable

Sense

Figure 14-3. Interrupt Controller Function Diagram

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