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CY7C65013-PVC bảng dữ liệu(PDF) 48 Page - Cypress Semiconductor

tên linh kiện CY7C65013-PVC
Giải thích chi tiết về linh kiện  USB Hub with Microcontroller
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CY7C65013-PVC bảng dữ liệu(HTML) 48 Page - Cypress Semiconductor

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CY7C65013
CY7C65113
Document #: 38-08002 Rev. *B
Page 48 of 51
22.0
Electrical Characteristics
fOSC = 6 MHz; Operating Temperature = 0 to 70°C, VCC = 4.0V to 5.25V
Parameter
Description
Conditions
Min.
Max.
Unit
General
VREF
Reference Voltage
3.3V ±5%
3.15
3.45
V
Vpp
Programming Voltage (disabled)
–0.4
0.4
V
I
CC
VCC Operating Current
No GPIO source current
50
mA
I
SB1
Supply Current—Suspend Mode
50
µA
Iref
VREF Operating Current
No USB Traffic[8]
10
mA
Iil
Input Leakage Current
Any pin
1
µA
USB Interface
Vdi
Differential Input Sensitivity
| (D+)–(D–) |
0.2
V
Vcm
Differential Input Common Mode Range
0.8
2.5
V
Vse
Single Ended Receiver Threshold
0.8
2.0
V
Cin
Transceiver Capacitance
20
pF
Ilo
Hi-Z State Data Line Leakage
0V < Vin < 3.3V
–10
10
µA
Rext
External USB Series Resistor
In series with each USB pin
19
21
Ω
RUUP
External Upstream USB Pull-up Resistor
1.5 k
Ω ±5%, D+ to V
REG
1.425
1.575
k
Ω
RUDN
External Downstream Pull-down Resistors 15 k
Ω ±5%, downstream USB pins
14.25
15.75
k
Ω
Power-on Reset
tvccs
VCC Ramp Rate
Linear ramp 0V to VCC
[9]
0100
ms
USB Upstream/Downstream Port
VUOH
Static Output High
15 k
Ω ±5% to Gnd
2.8
3.6
V
VUOL
Static Output Low
1.5 k
Ω ±5% to V
REF
0.3
V
ZO
USB Driver Output Impedance
Including Rext Resistor
28
44
Ω
General Purpose I/O (GPIO)
Rup
Pull-up Resistance (typical 14 k
Ω)
8.0
24.0
k
Ω
VITH
Input Threshold Voltage
All ports, low-to-high edge
20%
40%
VCC
VH
Input Hysteresis Voltage
All ports, high-to-low edge
2%
8%
VCC
VOL
Port 0,1,2,3 Output Low Voltage
IOL = 3 mA
IOL = 8 mA
0.4
2.0
V
V
VOH
Output High Voltage
IOH = 1.9 mA (all ports 0,1,2,3)
2.4
V
23.0
Switching Characteristics (fOSC = 6.0 MHz)
Parameter
Description
Min.
Max.
Unit
Clock Source
fOSC
Clock Rate
6 ±0.25%
MHz
tcyc
Clock Period
166.25
167.08
ns
tCH
Clock HIGH time
0.45 tCYC
ns
tCL
Clock LOW time
0.45 tCYC
ns
USB Full-speed Signaling[10]
trfs
Transition Rise Time
4
20
ns
tffs
Transition Fall Time
4
20
ns
trfmfs
Rise/Fall Time Matching; (tr/tf)
90
111
%
Notes:
8.
Add 18 mA per driven USB cable (upstream or downstream. This is based on transitions every 2 full-speed bit times on average.
9.
Power-on Reset occurs whenever the voltage on VCC is below approximately 2.5V.
10. Per Table 7-6 of revision 1.1 of USB specification.



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