CY7C65013
CY7C65113
Document #: 38-08002 Rev. *B
Page 10 of 51
4.2
I/O Register Summary
I/O registers are accessed via the I/O Read (IORD) and I/O Write (IOWR, IOWX) instructions. IORD reads data from the selected
port into the accumulator. IOWR performs the reverse; it writes data from the accumulator to the selected port. Indexed I/O Write
(IOWX) adds the contents of X to the address in the instruction to form the port address and writes data from the accumulator to
the specified port. Specifying address 0 (e.g., IOWX 0h) means the I/O register is selected solely by the contents of X.
All undefined registers are reserved. Do not write to reserved registers as this may cause an undefined operation or increased
current consumption during operation. When writing to registers with reserved bits, the reserved bits must be written with ‘0.’
XTALOUT
OUT
1
1
6-MHz crystal out.
VPP
29
19
Programming voltage supply, tie to ground during normal
operation.
VCC
48
28
Voltage supply.
GND
9, 16, 34, 40
4, 20
Ground.
VREF
IN
12, 37
3
External 3.3V supply voltage for the downstream differential
data output buffers and the D+ pull up.
Table 4-2. I/O Register Summary
Register Name
I/O Address
Read/Write
Function
Page
Port 0 Data
0x00
R/W
GPIO Port 0 Data
18
Port 1 Data
0x01
R/W
GPIO Port 1 Data
17
Port 2 Data
0x02
R/W
GPIO Port 2 Data
17
Port 3 Data
0x03
R/W
GPIO Port 3 Data
19
Port 0 Interrupt Enable
0x04
W
Interrupt Enable for Pins in Port 0
19
Port 1 Interrupt Enable
0x05
W
Interrupt Enable for Pins in Port 1
19
Port 2 Interrupt Enable
0x06
W
Interrupt Enable for Pins in Port 2
19
Port 3 Interrupt Enable
0x07
W
Interrupt Enable for Pins in Port 3
19
GPIO Configuration
0x08
R/W
GPIO Port Configurations
18
I2C Configuration
0x09
R/W
I2C Position Configuration
20
USB Device Address A
0x10
R/W
USB Device Address A
36
EP A0 Counter Register
0x11
R/W
USB Address A, Endpoint 0 Counter
38
EP A0 Mode Register
0x12
R/W
USB Address A, Endpoint 0 Configuration
37
EP A1 Counter Register
0x13
R/W
USB Address A, Endpoint 1 Counter
38
EP A1 Mode Register
0x14
R/W
USB Address A, Endpoint 1 Configuration
38
EP A2 Counter Register
0x15
R/W
USB Address A, Endpoint 2 Counter
38
EP A2 Mode Register
0x16
R/W
USB Address A, Endpoint 2 Configuration
38
USB Status & Control
0x1F
R/W
USB Upstream Port Traffic Status and Control
35
Global Interrupt Enable
0x20
R/W
Global Interrupt Enable
25
Endpoint Interrupt Enable
0x21
R/W
USB Endpoint Interrupt Enables
26
Interrupt Vector
0x23
R
Pending Interrupt Vector Read/Clear
27
Timer (LSB)
0x24
R
Lower Eight Bits of Free-running Timer (1 MHz)
20
Timer (MSB)
0x25
R
Upper Four Bits of Free-running Timer
20
WDR Clear
0x26
W
Watchdog Reset Clear
17
I2C Control & Status
0x28
R/W
I2C Status and Control
21
I2C Data
0x29
R/W
I2C Data
23
Table 4-1. Pin Assignments (continued)
Name
I/O
48-pin
28-pin
Description
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