CY7C65013
CY7C65113
Document #: 38-08002 Rev. *B
Page 17 of 51
7.2
Watchdog Reset
The WDR occurs when the internal Watchdog Timer rolls over. Writing any value to the write-only Watchdog Reset Clear Register
(Figure 7-1) clears the timer. The timer rolls over and WDR occurs if it is not cleared within tWATCH of the last clear (see Section
23.0 for the value of tWATCH). Bit 6 of the Processor Status and Control Register (Figure 13-1) is set to record this event (the
register contents are set to 010X0001 by the WDR). A Watchdog Timer Reset lasts for 2 ms, after which the microcontroller begins
execution at ROM address 0x0000.
The USB transmitter is disabled by a Watchdog Reset because the USB Device Address Registers are cleared (see Section
17.1). Otherwise, the USB Controller would respond to all address 0 transactions.
It is possible for the WDR bit of the Processor Status and Control Register (Figure 13-1) to be set following a POR event. If a
firmware interrogates the Processor Status and Control Register for a set condition on the WDR bit, the WDR bit should be ignored
if the POR bit is set (Bit 3 of the Processor Status and Control Register).
8.0
Suspend Mode
The CY7C65x13 can be placed into a low-power state by setting the Suspend bit of the Processor Status and Control register.
All logic blocks in the device are turned off except the GPIO interrupt logic and the USB receiver. The clock oscillator and PLL,
as well as the free-running and Watchdog timers, are shut down. Only the occurrence of an enabled GPIO interrupt or non-idle
bus activity at a USB upstream or downstream port wakes the part out of suspend. The Run bit in the Processor Status and
Control Register must be set to resume a part out of suspend.
The clock oscillator restarts immediately after exiting suspend mode. The microcontroller returns to a fully functional state 1 ms
after the oscillator is stable. The microcontroller executes the instruction following the I/O write that placed the device into suspend
mode before servicing any interrupt requests.
The GPIO interrupt allows the controller to wake-up periodically and poll system components while maintaining a very low average
power consumption. To achieve the lowest possible current during suspend mode, all I/O should be held at VCC or Gnd. Note:
This also applies to internal port pins that may not be bonded in a particular package.
Typical code for entering suspend is shown below:
...
; All GPIO set to low-power state (no floating pins)
...
; Enable GPIO interrupts if desired for wake-up
mov a, 09h
; Set suspend and run bits
iowr FFh
; Write to Status and Control Register – Enter suspend, wait for USB activity (or GPIO Interrupt)
nop
; This executes before any ISR
...
; Remaining code for exiting suspend routine.
Last write to
Watchdog Timer
Register
No write to WDT
register, so WDR
goes HIGH
Execution begins at
Reset Vector 0x0000
tWATCH
2 ms
Figure 7-1. Watchdog Reset (Address 0x26)
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