CY7C65013
CY7C65113
Document #: 38-08002 Rev. *B
Page 23 of 51
The I2C clock (SCL) is connected to bit 0 of either GPIO port 1 or GPIO port 2, and the I2C SDA data is connected to bit 1 of
either GPIO port 1 or GPIO port 2. The port selection is determined by settings in the I2C Port Configuration Register (Section
11.0). Once the I2C-compatible functionality is enabled by setting the I2C Enable bit of the I2C Status and Control Register (bit 0,
Figure 12-2), the two LSB ([1:0]) of the corresponding GPIO port is placed in Open Drain mode, regardless of the settings of the
GPIO Configuration Register. In Open Drain mode, the GPIO pin outputs LOW if the pin’s Data Register is ‘0’, and the pin is in
Hi-Z mode if the pin’s Data Register is ‘1’. The electrical characteristics of the I2C-compatible interface is the same as that of
GPIO ports 1 and 2. Note that the IOL (max) is 2 mA @ VOL = 2.0V for ports 1 and 2.
All control of the I2C clock (SCL) and data (SDA) lines is performed by the I2C-compatible block.
Bits [7..0] : I2C Data
Contains the 8-bit data on the I2C Bus.
The I2C Status and Control register bits are defined in Table 12-1, with a more detailed description following.
Bit 7 : MSTR Mode
Setting this bit to 1 causes the I2C-compatible block to initiate a master mode transaction by sending a start bit and
transmitting the first data byte from the data register (this typically holds the target address and R/W bit). Subsequent bytes
are initiated by setting the Continue bit, as described below.
Clearing this bit (set to 0) causes the GPIO pins to operate normally.
In master mode, the I2C-compatible block generates the clock (SCK), and drives the data line as required depending on
transmit or receive state. The I2C-compatible block performs any required arbitration and clock synchronization. IN the
event of a loss of arbitration, this MSTR bit is cleared, the ARB Lost bit is set, and an interrupt is generated by the
I2C Data
Address 0x29
Bit #
7
6
5432
10
Bit Name
I2C Data 7
I2C Data 6
I2C Data 5
I2C Data 4
I2C Data 3
I2C Data 2
I2C Data 1
I2C Data 0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
X
X
XXX
XXX
Figure 12-1. I2C Data Register
I2C Status and Control
Address 0x28
Bit #
7
6
5432
10
Bit Name
MSTR Mode Continue/Bu
sy
Xmit Mode
ACK
Addr
ARB
Lost/Restart
Received
Stop
I2C Enable
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0000
00
Figure 12-2. I2C Status and Control Register
Table 12-1. I2C Status and Control Register Bit Definitions
Bit
Name
Description
0I2C Enable
When set to ‘1’, the I2C-compatible function is enabled. When cleared, I2C GPIO pins operate
normally.
1
Received Stop
Reads 1 only in slave receive mode, when I2C Stop bit detected (unless firmware did not ACK the
last transaction).
2
ARB Lost/Restart
Reads 1 to indicate master has lost arbitration. Reads 0 otherwise.
Write to 1 in master mode to perform a restart sequence (also set Continue bit).
3
Addr
Reads 1 during first byte after start/restart in slave mode, or if master loses arbitration.
Reads 0 otherwise. This bit should always be written as 0.
4
ACK
In receive mode, write 1 to generate ACK, 0 for no ACK.
In transmit mode, reads 1 if ACK was received, 0 if no ACK received.
5
Xmit Mode
Write to 1 for transmit mode, 0 for receive mode.
6
Continue/Busy
Write 1 to indicate ready for next transaction.
Reads 1 when I2C-compatible block is busy with a transaction, 0 when transaction is complete.
7
MSTR Mode
Write to 1 for master mode, 0 for slave mode. This bit is cleared if master loses arbitration.
Clearing from 1 to 0 generates Stop bit.
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