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CY7C65013
CY7C65113
Document #: 38-08002 Rev. *B
Page 21 of 51
10.0
12-bit Free-Running Timer
The 12-bit timer operates with a 1-
µs tick, provides two interrupts (128µs and 1.024ms) and allows the firmware to directly time
events that are up to 4 ms in duration. The lower eight bits of the timer can be read directly by the firmware. Reading the lower
eight bits latches the upper four bits into a temporary register. When the firmware reads the upper four bits of the timer, it is actually
reading the count stored in the temporary register. The effect of this is to ensure a stable 12-bit timer value can be read, even
when the two reads are separated in time.
Bit [7:0]: Timer lower eight bits.
Bit [3:0]: Timer higher nibble
Bit [7:4]: Reserved.
Port 2 Interrupt Enable
Address 0x06
Bit #
765
43
210
Bit Name
P0.7 Intr
Enable
P0.6 Intr
Enable
P0.5 Intr
Enable
P0.4 Intr
Enable
P0.3 Intr
Enable
Reserved
Reserved
Reserved
Read/Write
W
WWW
WWW
W
Reset
000
00
000
Figure 9-9. Port 2 Interrupt Enable
Port 3 Interrupt Enable
Address 0x07
Bit #
765
43
210
Bit Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
P3.1 Intr
Enable
P0.3 Intr
Enable
Read/Write
W
WWW
WWW
W
Reset
000
00
000
Figure 9-10. Port 3 Interrupt Enable
Timer LSB
Address 0x24
Bit #
7
6
5432
10
Bit Name
Timer Bit 7
TimerBit 6
Timer Bit 5
Timer Bit 4
Timer Bit 3
Timer Bit 2
Timer Bit 1
Timer Bit 0
Read/Write
R
R
RRR
RRR
Reset
0
0
0000
00
Figure 10-1. Timer LSB Register
Timer MSB
Address 0x25
Bit #
7
6
5432
10
Bit Name
Reserved
Reserved
Reserved
Reserved
Timer Bit 11 Timer Bit 10
Timer Bit 9
Timer Bit 8
Read/Write
–
–
–
–
R
R
R
R
Reset
0
0
0000
00
Figure 10-2. Timer MSB Register
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