CY7C65013
CY7C65113
Document #: 38-08002 Rev. *B
Page 22 of 51
11.0
I2C Configuration Register
Internal hardware supports communication with external devices through an I2C-compatible interface. I2C-compatible function is
discussed in detail in Section 12.0.[3] The I2C Position bit (Bit 7, Figure 11-1) and I2C Port Width bit (Bit 1, Figure 11-1) select the
locations of the SCL (clock) and SDA (data) pins, either on Port 1 or Port 2 as shown in Table 11-1. These bits are cleared on
reset. When the GPIO is configured for I2C function, the internal pull ups on the pins are disabled. Addition of an external weak
pull-up resistors on SCL and SDA is recommended
.
12.0
I2C-compatible Controller
The I2C-compatible block provides a versatile two-wire communication with external devices, supporting master, slave, and
multi-master modes of operation. The I2C-compatible block functions by handling the low-level signaling in hardware, and issuing
interrupts as needed to allow firmware to take appropriate action during transactions. While waiting for firmware response, the
hardware keeps the I2C-compatible bus idle if necessary.
The I2C-compatible block generates an interrupt to the microcontroller at the end of each received or transmitted byte, when a
stop bit is detected by the slave when in receive mode, or when arbitration is lost. Details of the interrupt responses are given in
Section 14.8.
The I2C-compatible interface consists of two registers, an I2C Data Register (Figure 12-1) and an I2C Status and Control Register
(Figure 12-2). The I2C Data Register is implemented as separate read and write registers. Generally, the I2C Status and Control
Register should only be monitored after the I2C interrupt, as all bits are valid at that time. Polling this register at other times could
read misleading bit status if a transaction is underway.
Note:
3.
I2C-compatible function must be separately enabled, as described in Section 12.0.
I2C Configuration
Address 0x09
Bit #
7
6
5432
10
Bit Name
I2C Position
Reserved
Reserved
Reserved
Reserved
Reserved
I2C Port
Width
Reserved
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0000
00
Figure 11-1. I2C Configuration Register
Table 11-1. I2C Port Configuration
I2C Position (Bit7, Figure 11-1)I2C Port Width (Bit1, Figure 11-1)I2C Position
Don’t Care
1
I2C on P2[1:0], 0:SCL, 1:SDA
00
I2C on P1[1:0], 0:SCL, 1:SDA
10
I2C on P2[1:0], 0:SCL, 1:SDA
10
9
7
85
64
3
2
1 MHz clock
1.024-ms interrupt
128-
µs interrupt
To Timer Registers
8
1
0
11
L1 L0
L2
L3
D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Figure 10-3. Timer Block Diagram
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