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CY7C65013-PVC bảng dữ liệu(PDF) 43 Page - Cypress Semiconductor

tên linh kiện CY7C65013-PVC
Giải thích chi tiết về linh kiện  USB Hub with Microcontroller
PDF  51 Pages
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nhà sản xuất  CYPRESS [Cypress Semiconductor]
Trang chủ  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C65013-PVC bảng dữ liệu(HTML) 43 Page - Cypress Semiconductor

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CY7C65013
CY7C65113
Document #: 38-08002 Rev. *B
Page 43 of 51
7. The entire Endpoint 0 mode register and the Count register are locked to CPU writes at the end of any transaction to that
endpoint in which an ACK is transferred. These registers are only unlocked by a CPU read of the register, which should be
done by the firmware only after the transaction is complete. This represents about a 1-
µs window in which the CPU is locked
from register writes to these USB registers. Normally the firmware should perform a register read at the beginning of the
Endpoint ISRs to unlock and get the mode register information. The interlock on the Mode and Count registers ensures that
the firmware recognizes the changes that the SIE might have made during the previous transaction. Note that the setup bit of
the mode register is NOT locked. This means that before writing to the mode register, firmware must first read the register to
make sure that the setup bit is not set (which indicates a setup was received, while processing the current USB request). This
read will of course unlock the register. So care must be taken not to overwrite the register elsewhere
.
Table 18-3. Details of Modes for Differing Traffic Conditions (see Table 18-2 for the decode legend)
SETUP (if accepting SETUPs)
Properties of Incoming Packet
Changes made by SIE to Internal Registers and Mode Bits
Mode Bits
token
count
buffer
dval
DTOG
DVAL
COUNT
Setup
In
Out
ACK
Mode Bits
Response
Intr
See Table 18-1
Setup
<= 10
data
valid
updates
1
updates
1
UC
UC
1
0
001ACK
yes
See Table 18-1
Setup
> 10
junk
x
updates
updates
updates
1
UC
UC
UC
NoChange
ignore
yes
See Table 18-1
Setup
x
junk
invalid
updates
0
updates
1
UC
UC
UC
NoChange
ignore
yes
Properties of Incoming Packet
Changes made by SIE to Internal Registers and Mode Bits
Mode Bits
token
count
buffer
dval
DTOG
DVAL
COUNT
Setup
In
Out
ACK
Mode Bits
Response
Intr
DISABLED
0
0
0
0
x
x
UC
x
UC
UC
UC
UC
UC
UC
UC
NoChange
ignore
no
Nak In/Out
0
0
0
1
Out
x
UC
x
UC
UC
UC
UC
UC
1
UC
NoChange
NAK
yes
0
0
0
1
In
x
UC
x
UC
UC
UC
UC
1
UC
UC
NoChange
NAK
yes
Ignore In/Out
0
1
0
0
Out
x
UC
x
UC
UC
UC
UC
UC
UC
UC
NoChange
ignore
no
0
1
0
0
In
x
UC
x
UC
UC
UC
UC
UC
UC
UC
NoChange
ignore
no
Stall In/Out
0
0
1
1
Out
x
UC
x
UC
UC
UC
UC
UC
1
UC
NoChange
Stall
yes
0
0
1
1
In
x
UC
x
UC
UC
UC
UC
1
UC
UC
NoChange
Stall
yes
CONTROL WRITE
Properties of Incoming Packet
Changes made by SIE to Internal Registers and Mode Bits
Mode Bits
token
count
buffer
dval
DTOG
DVAL
COUNT
Setup
In
Out
ACK
Mode Bits
Response
Intr
Normal Out/premature status In
1
0
1
1
Out
<= 10
data
valid
updates
1
updates
UC
UC
1
1
1
010ACK
yes
1
0
1
1
Out
> 10
junk
x
updates
updates
updates
UC
UC
1
UC
NoChange
ignore
yes
1
0
1
1
Out
x
junk
invalid
updates
0
updates
UC
UC
1
UC
NoChange
ignore
yes
1
0
1
1
In
x
UC
x
UC
UC
UC
UC
1
UC
1
NoChange
TX 0
yes
NAK Out/premature status In
1
0
1
0
Out
<= 10
UC
valid
UC
UC
UC
UC
UC
1
UC
NoChange
NAK
yes
1
0
1
0
Out
> 10
UC
x
UC
UC
UC
UC
UC
UC
UC
NoChange
ignore
no
1
0
1
0
Out
x
UC
invalid
UC
UC
UC
UC
UC
UC
UC
NoChange
ignore
no
1
0
1
0
In
x
UC
x
UC
UC
UC
UC
1
UC
1
NoChange
TX 0
yes
Status In/extra Out
0
1
1
0
Out
<= 10
UC
valid
UC
UC
UC
UC
UC
1
UC
0
011Stall
yes
0
1
1
0
Out
> 10
UC
x
UC
UC
UC
UC
UC
UC
UC
NoChange
ignore
no
0
1
1
0
Out
x
UC
invalid
UC
UC
UC
UC
UC
UC
UC
NoChange
ignore
no
0
1
1
0
In
x
UC
x
UC
UC
UC
UC
1
UC
1
NoChange
TX 0
yes
CONTROL READ
Properties of Incoming Packet
Changes made by SIE to Internal Registers and Mode Bits
Mode Bits
token
count
buffer
dval
DTOG
DVAL
COUNT
Setup
In
Out
ACK
Mode Bits
Response
Intr
Normal In/premature status Out
1
1
1
1
Out
2
UC
valid
1
1
updates
UC
UC
1
1
NoChange
ACK
yes
1
1
1
1
Out
2
UC
valid
0
1
updates
UC
UC
1
UC
0
011Stall
yes
1
1
1
1
Out
!=2
UC
valid
updates
1
updates
UC
UC
1
UC
0
011Stall
yes
1
1
1
1
Out
> 10
UC
x
UC
UC
UC
UC
UC
UC
UC
NoChange
ignore
no
1
1
1
1
Out
x
UC
invalid
UC
UC
UC
UC
UC
UC
UC
NoChange
ignore
no
1
1
1
1
In
x
UC
x
UC
UC
UC
UC
1
UC
1
1
110ACK (back)
yes



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