CY7C65013
CY7C65113
Document #: 38-08002 Rev. *B
Page 19 of 51
Special care should be taken with any unused GPIO data bits. An unused GPIO data bit, either a pin on the chip or a port bit that
is not bonded on a particular package, must not be left floating when the device enters the suspend state. If a GPIO data bit is
left floating, the leakage current caused by the floating bit may violate the suspend current limitation specified by the USB
Specifications. If a ‘1’ is written to the unused data bit and the port is configured with open drain outputs, the unused data bit
remains in an indeterminate state. Therefore, if an unused port bit is programmed in open-drain mode, it must be written with a
‘0.’ Notice that the CY7C65113 always requires that P1[7:3], P2[7:0], and P3[7:0] be written with a ‘0.’ When the CY7C65013 is
used, the P1[3], P2[2:0], and P3[7:2] should be written with a ‘0.’
A read from a GPIO port always returns the present state of the voltage at the pin, independent of the settings in the Port Data
Registers. During reset, all of the GPIO pins are set to a high-impedance input state. Writing a ‘0’ to a GPIO pin drives the pin
LOW. In this state, a ‘0’ is always read on that GPIO pin unless an external source overdrives the internal pull-down device.
9.1
GPIO Configuration Port
Every GPIO port can be programmed as inputs with internal pull-ups, outputs LOW or HIGH, or Hi-Z (floating, the pin is not driven
internally). In addition, the interrupt polarity for each port can be programmed. The Port Configuration bits (Figure 9-6) and the
Interrupt Enable bit (Figure 9-7 through Figure 9-10) determine the interrupt polarity of the port pins
.
As shown in Table 9-1 below, a positive polarity on an input pin represents a rising edge interrupt (LOW to HIGH), and a negative
polarity on an input pin represents a falling edge interrupt (HIGH to LOW).
The GPIO interrupt is generated when all of the following conditions are met: the Interrupt Enable bit of the associated Port
Interrupt Enable Register is enabled, the GPIO Interrupt Enable bit of the Global Interrupt Enable Register (Figure 14-1) is
enabled, the Interrupt Enable Sense (bit 2, Figure 13-1) is set, and the GPIO pin of the port sees an event matching the interrupt
polarity.
The driving state of each GPIO pin is determined by the value written to the pin’s Data Register (Figure 9-2 through Figure 9-5)
and by its associated Port Configuration bits as shown in the GPIO Configuration Register (Figure 9-6). These ports are
configured on a per-port basis, so all pins in a given port are configured together. The possible port configurations are detailed
in Table 9-1. As shown in this table below, when a GPIO port is configured with CMOS outputs, interrupts from that port are
disabled.
During reset, all of the bits in the GPIO Configuration Register are written with ‘0’ to select Hi-Z mode for all GPIO ports as the
default configuration.
Port 3 Data
Address 0x03
Bit #
765
43
210
Bit Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
P3.1
P3.0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
111
11
111
Figure 9-5. Port 3 Data
GPIO Configuration
Address 0x08
Bit #
765
43
210
Bit Name
Port 3
Config Bit 1
Port 3
Config Bit 0
Port 2
Config Bit 1
Port 2
Config Bit 0
Port 1
Config Bit 1
Port 1
Config Bit 0
Port 0
Config Bit 1
Port 0
Config Bit 0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
000
00
000
Figure 9-6. GPIO Configuration Register
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