TMS320DM355CZCEA13 datasheet(130/163 Pages) TI1

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VCLKIN(A)

(Positive Edge Clocking)

VCLKIN(A)

(Negative Edge Clocking)

VCTL(B)

A. VCLKIN=PCLKorEXTCLK

B. VCTL=HSYNC,VSYNC,andFIELD

VCLKIN(A)

(Positive Edge Clocking)

VCLKIN(A)

(Negative Edge Clocking)

VCTL(B)

A. VCLKIN=PCLKorEXTCLK

B. VCTL=HSYNC,VSYNC,FIELD,andLCD_OE

C. VDATA=COUT[7:0],YOUT[7:0],R[7:3],G[7:2],andB[7:3]

VDATA(C)

TMS320DM355

SPRS463G – SEPTEMBER 2007 – REVISED JUNE 2010

www.ti.com

Figure 5-28. VPBE Input Timing With Respect to PCLK and EXTCLK

Table 5-23. Switching Characteristics Over Recommended Operating Conditions for VPBE Control and

Data Output With Respect to PCLK and EXTCLK(1) (2) (3) (see Figure 5-29)

DM355

NO.

PARAMETER

UNIT

MIN

MAX

td(VCLKIN-VCTLV)

Delay time, VCLKIN edge to VCTL valid

13.3

td(VCLKIN-VCTLIV)

Delay time, VCLKIN edge to VCTL invalid

td(VCLKIN-VDATAV)

Delay time, VCLKIN edge to VDATA valid

13.3

td(VCLKIN-VDATAIV)

Delay time, VCLKIN edge to VDATA invalid

(1)

The VPBE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the

rising edge of VCLKIN is referenced. When in negative edge clocking mode, the falling edge of VCLKIN is referenced.

(2)

VCLKIN = PCLK or EXTCLK

(3)

VCTL = HSYNC, VSYNC, FIELD, and LCD_OE

Figure 5-29. VPBE Control and Data Output With Respect to PCLK and EXTCLK

130

DM355 Peripheral Information and Electrical Specifications

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