TMS320DM355CZCEA13 datasheet(102/163 Pages) TI1

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TransmissionLine

4.0pF

1.85pF

Z0=50 Ω

(seenote)

Tester PinElectronics

Data SheetTimingReferencePoint

Output

Under

Test

42 Ω

3.5nH

DevicePin

(seenote)

Vref

Vref =VIL MAX(orVOL MAX)

Vref =VIH MIN(orVOH MIN)

TMS320DM355

SPRS463G – SEPTEMBER 2007 – REVISED JUNE 2010

www.ti.com

DM355 Peripheral Information and Electrical Specifications

5.1

Parameter Information Device-Specific Information

The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its

transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to

produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to

add or subtract the transmission line delay (2 ns or longer) from the data sheet timings.

Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the

device pin.

Figure 5-1. Test Load Circuit for AC Timing Measurements

The load capacitance value stated is only for characterization and measurement of AC timing signals. This

load capacitance value does not indicate the maximum load the device is capable of driving.

5.1.1

Signal Transition Levels

All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels. For 3.3 V I/O,

Vref = 1.65 V. For 1.8 V I/O, Vref = 0.9 V.

Figure 5-2. Input and Output Voltage Reference Levels for AC Timing Measurements

All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks,

VOLMAX and VOH MIN for output clocks.

Figure 5-3. Rise and Fall Transition Time Voltage Reference Levels

5.1.2

Timing Parameters and Board Routing Analysis

The timing parameter values specified in this data sheet do not include delays by board routings. As a

good board design practice, such delays must always be taken into account. Timing values may be

adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer

information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS

models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing

Analysis application report (literature number SPRA839). If needed, external logic hardware such as

buffers may be used to compensate any timing differences.

102

DM355 Peripheral Information and Electrical Specifications

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