MC9S08DZ96F2CLL datasheet(161/458 Pages) FREESCALE

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Chapter 7 Central Processor Unit (S08CPUV5)

MC9S08DZ128 Series Data Sheet, Rev. 1

Freescale Semiconductor

161

TXS

Transfer Index Reg. to SP

← (H:X) – $0001

INH

–11–

––––

WAIT

Enable Interrupts; Wait for Interrupt

I bit

← 0; Halt CPU

INH

fp...

–11–

0–––

Source Form: Everything in the source forms columns, except expressions in italic characters, is literal information which must appear in the

assembly source ﬁle exactly as shown. The initial 3- to 5-letter mnemonic and the characters (# , ( ) and +) are always a literal characters.

Any label or expression that evaluates to a single integer in the range 0-7.

opr8i

Any label or expression that evaluates to an 8-bit immediate value.

opr16i

Any label or expression that evaluates to a 16-bit immediate value.

opr8a

Any label or expression that evaluates to an 8-bit direct-page address ($00xx).

opr16a

Any label or expression that evaluates to a 16-bit address.

oprx8

Any label or expression that evaluates to an unsigned 8-bit value, used for indexed addressing.

oprx16

Any label or expression that evaluates to a 16-bit value, used for indexed addressing.

rel

Any label or expression that refers to an address that is within –128 to +127 locations from the start of the next instruction.

Operation Symbols:

Accumulator

CCR

Condition code register

Index register high byte

Memory location

Any bit

opr

Operand (one or two bytes)

Program counter

PCH

Program counter high byte

PCL

Program counter low byte

rel

Relative program counter offset byte

Stack pointer

SPL

Stack pointer low byte

Index register low byte

Logical AND

Logical OR

⊕

Logical EXCLUSIVE OR

( )

Contents of

Add

–

Subtract, Negation (two’s complement)

Multiply

Divide

Immediate value

←

Loaded with

Concatenated with

Addressing Modes:

DIR

Direct addressing mode

EXT

Extended addressing mode

IMM

Immediate addressing mode

INH

Inherent addressing mode

Indexed, no offset addressing mode

IX1

Indexed, 8-bit offset addressing mode

IX2

Indexed, 16-bit offset addressing mode

IX+

Indexed, no offset, post increment addressing mode

IX1+

Indexed, 8-bit offset, post increment addressing mode

REL

Relative addressing mode

SP1

Stack pointer, 8-bit offset addressing mode

SP2

Stack pointer 16-bit offset addressing mode

Cycle-by-Cycle Codes:

Free cycle. This indicates a cycle where the CPU

does not require use of the system buses. An f

cycle is always one cycle of the system bus clock

and is always a read cycle.

Program fetch; read from next consecutive

location in program memory

Read 8-bit operand

Push (write) one byte onto stack

Pop (read) one byte from stack

Read vector from $FFxx (high byte ﬁrst)

Write 8-bit operand

CCR Bits:

Overﬂow bit

Half-carry bit

Interrupt mask

Negative bit

Zero bit

Carry/borrow bit

CCR Effects:

↕

Set or cleared

–

Not affected

Undeﬁned

Table 7-2. Instruction Set Summary (Sheet 9 of 9)

Source

Form

Operation

Object Code

Cyc-by-Cyc

Details

Affect

on CCR

V 1 1 H

I N Z C

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