MC9S08DZ96F2CLL datasheet(126/458 Pages) FREESCALE

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Chapter 6 Parallel Input/Output Control

MC9S08DZ128 Series Data Sheet, Rev. 1

126

Freescale Semiconductor

6.5.7

Port G Registers

Port G is controlled by the registers listed below.

6.5.7.1

Port G Data Register (PTGD)

6.5.7.2

Port G Data Direction Register (PTGDD)

76543210

PTGD7

PTGD6

PTGD5

PTGD4

PTGD3

PTGD2

PTGD1

PTGD0

Reset:

00000000

Figure 6-42. Port G Data Register (PTGD)

Table 6-40. PTGD Register Field Descriptions

Field

Description

7:0

PTGD[7:0]

Port G Data Register Bits — For port G pins that are inputs, reads return the logic level on the pin. For port G

pins that are conﬁgured as outputs, reads return the last value written to this register.

Writes are latched into all bits of this register. For port G pins that are conﬁgured as outputs, the logic level is

driven out the corresponding MCU pin.

Reset forces PTGD to all 0s, but these 0s are not driven out the corresponding pins because reset also

conﬁgures all port pins as high-impedance inputs with pull-ups disabled.

76543210

PTGDD7

PTGDD6

PTGDD5

PTGDD4

PTGDD3

PTGDD2

PTGDD1

PTGDD0

Reset:

00000000

Figure 6-43. Port G Data Direction Register (PTGDD)

Table 6-41. PTGDD Register Field Descriptions

Field

Description

7:0

PTGDD[7:0]

Data Direction for Port G Bits — These read/write bits control the direction of port G pins and what is read for

PTGD reads.

0 Input (output driver disabled) and reads return the pin value.

1 Output driver enabled for port G bit n and PTGD reads return the contents of PTGDn.

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