MC9S08DZ96F2CLL datasheet(123/458 Pages) FREESCALE

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Chapter 6 Parallel Input/Output Control

MC9S08DZ128 Series Data Sheet, Rev. 1

Freescale Semiconductor

123

6.5.6

Port F Registers

Port F is controlled by the registers listed below.

6.5.6.1

Port F Data Register (PTFD)

6.5.6.2

Port F Data Direction Register (PTFDD)

76543210

PTFD7

PTFD6

PTFD5

PTFD4

PTFD3

PTFD2

PTFD1

PTFD0

Reset:

00000000

Figure 6-37. Port F Data Register (PTFD)

Table 6-35. PTFD Register Field Descriptions

Field

Description

7:0

PTFD[7:0]

Port F Data Register Bits — For port F pins that are inputs, reads return the logic level on the pin. For port F

pins that are conﬁgured as outputs, reads return the last value written to this register.

Writes are latched into all bits of this register. For port F pins that are conﬁgured as outputs, the logic level is

driven out the corresponding MCU pin.

Reset forces PTFD to all 0s, but these 0s are not driven out the corresponding pins because reset also conﬁgures

all port pins as high-impedance inputs with pull-ups disabled.

76543210

PTFDD7

PTFDD6

PTFDD5

PTFDD4

PTFDD3

PTFDD2

PTFDD1

PTFDD0

Reset:

00000000

Figure 6-38. Port F Data Direction Register (PTFDD)

Table 6-36. PTFDD Register Field Descriptions

Field

Description

7:0

PTFDD[7:0]

Data Direction for Port F Bits — These read/write bits control the direction of port F pins and what is read for

PTFD reads.

0 Input (output driver disabled) and reads return the pin value.

1 Output driver enabled for port F bit n and PTFD reads return the contents of PTFDn.

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