MC9S08DZ96F2CLL datasheet(116/458 Pages) FREESCALE

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Chapter 6 Parallel Input/Output Control

MC9S08DZ128 Series Data Sheet, Rev. 1

116

Freescale Semiconductor

6.5.4

Port D Registers

Port D is controlled by the registers listed below.

6.5.4.1

Port D Data Register (PTDD)

6.5.4.2

Port D Data Direction Register (PTDDD)

76543210

PTDD7

PTDD6

PTDD5

PTDD4

PTDD3

PTDD2

PTDD1

PTDD0

Reset:

00000000

Figure 6-24. Port D Data Register (PTDD)

Table 6-22. PTDD Register Field Descriptions

Field

Description

7:0

PTDD[7:0]

Port D Data Register Bits — For port D pins that are inputs, reads return the logic level on the pin. For port D

pins that are conﬁgured as outputs, reads return the last value written to this register.

Writes are latched into all bits of this register. For port D pins that are conﬁgured as outputs, the logic level is

driven out the corresponding MCU pin.

Reset forces PTDD to all 0s, but these 0s are not driven out the corresponding pins because reset also

conﬁgures all port pins as high-impedance inputs with pull-ups/pull-downs disabled.

76543210

PTDDD7

PTDDD6

PTDDD5

PTDDD4

PTDDD3

PTDDD2

PTDDD1

PTDDD0

Reset:

00000000

Figure 6-25. Port D Data Direction Register (PTDDD)

Table 6-23. PTDDD Register Field Descriptions

Field

Description

7:0

PTDDD[7:0]

Data Direction for Port D Bits — These read/write bits control the direction of port D pins and what is read for

PTDD reads.

0 Input (output driver disabled) and reads return the pin value.

1 Output driver enabled for port D bit n and PTDD reads return the contents of PTDDn.

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