MC9S08DZ96F2CLL datasheet(106/458 Pages) FREESCALE

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Chapter 6 Parallel Input/Output Control

MC9S08DZ128 Series Data Sheet, Rev. 1

106

Freescale Semiconductor

6.5.1.3

Port A Pull Enable Register (PTAPE)

NOTE

Pull-down devices only apply when using pin interrupt functions, when

corresponding edge select and pin select functions are conﬁgured.

6.5.1.4

Port A Slew Rate Enable Register (PTASE)

Note: Slew rate reset default values may differ between engineering samples and ﬁnal production parts. Always initialize slew

rate control to the desired value to ensure correct operation.

76543210

PTAPE7

PTAPE6

PTAPE5

PTAPE4

PTAPE3

PTAPE2

PTAPE1

PTAPE0

Reset:

00000000

Figure 6-5. Internal Pull Enable for Port A Register (PTAPE)

Table 6-3. PTAPE Register Field Descriptions

Field

Description

7:0

PTAPE[7:0]

Internal Pull Enable for Port A Bits — Each of these control bits determines if the internal pull-up or pull-down

device is enabled for the associated PTA pin. For port A pins that are conﬁgured as outputs, these bits have no

effect and the internal pull devices are disabled.

0 Internal pull-up/pull-down device disabled for port A bit n.

1 Internal pull-up/pull-down device enabled for port A bit n.

76543210

PTASE7

PTASE6

PTASE5

PTASE4

PTASE3

PTASE2

PTASE1

PTASE0

Reset:

00000000

Figure 6-6. Slew Rate Enable for Port A Register (PTASE)

Table 6-4. PTASE Register Field Descriptions

Field

Description

7:0

PTASE[7:0]

Output Slew Rate Enable for Port A Bits — Each of these control bits determines if the output slew rate control

is enabled for the associated PTA pin. For port A pins that are conﬁgured as inputs, these bits have no effect.

0 Output slew rate control disabled for port A bit n.

1 Output slew rate control enabled for port A bit n.

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