MC9S08DZ96F2CLL datasheet(105/458 Pages) FREESCALE

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Chapter 6 Parallel Input/Output Control

MC9S08DZ128 Series Data Sheet, Rev. 1

Freescale Semiconductor

105

Semiconductor-provided equate or header ﬁle normally is used to translate these names into the

appropriate absolute addresses.

6.5.1

Port A Registers

Port A is controlled by the registers listed below.

6.5.1.1

Port A Data Register (PTAD)

6.5.1.2

Port A Data Direction Register (PTADD)

76543210

PTAD7

PTAD6

PTAD5

PTAD4

PTAD3

PTAD2

PTAD1

PTAD0

Reset:

00000000

Figure 6-3. Port A Data Register (PTAD)

Table 6-1. PTAD Register Field Descriptions

Field

Description

7:0

PTAD[7:0]

Port A Data Register Bits — For port A pins that are inputs, reads return the logic level on the pin. For port A

pins that are conﬁgured as outputs, reads return the last value written to this register.

Writes are latched into all bits of this register. For port A pins that are conﬁgured as outputs, the logic level is

driven out the corresponding MCU pin.

Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also conﬁgures

all port pins as high-impedance inputs with pull-ups/pull-downs disabled.

76543210

PTADD7

PTADD6

PTADD5

PTADD4

PTADD3

PTADD2

PTADD1

PTADD0

Reset:

00000000

Figure 6-4. Port A Data Direction Register (PTADD)

Table 6-2. PTADD Register Field Descriptions

Field

Description

7:0

PTADD[7:0]

Data Direction for Port A Bits — These read/write bits control the direction of port A pins and what is read for

PTAD reads.

0 Input (output driver disabled) and reads return the pin value.

1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn.

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