MC9S08DZ96F2CLL datasheet(265/458 Pages) FREESCALE

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Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)

MC9S08DZ128 Series Data Sheet, Rev. 1

Freescale Semiconductor

265

12.3.5

MSCAN Receiver Interrupt Enable Register (CANRIER)

This register contains the interrupt enable bits for the interrupt ﬂags described in the CANRFLG register.

NOTE

The CANRIER register is held in the reset state when the initialization mode

is active (INITRQ=1 and INITAK=1). This register is writable when not in

initialization mode (INITRQ=0 and INITAK=0).

The RSTATE[1:0], TSTATE[1:0] bits are not affected by initialization

mode.

Read: Anytime

Write: Anytime when not in initialization mode

OVRIF

Overrun Interrupt Flag — This ﬂag is set when a data overrun condition occurs. If not masked, an error interrupt

is pending while this ﬂag is set.

No data overrun condition

A data overrun detected

RXF2

Receive Buffer Full Flag — RXF is set by the MSCAN when a new message is shifted in the receiver FIFO. This

ﬂag indicates whether the shifted buffer is loaded with a correctly received message (matching identiﬁer,

matching cyclic redundancy code (CRC) and no other errors detected). After the CPU has read that message

from the RxFG buffer in the receiver FIFO, the RXF ﬂag must be cleared to release the buffer. A set RXF ﬂag

prohibits the shifting of the next FIFO entry into the foreground buffer (RxFG). If not masked, a receive interrupt

is pending while this ﬂag is set.

No new message available within the RxFG

The receiver FIFO is not empty. A new message is available in the RxFG

1 Redundant Information for the most critical CAN bus status which is “bus-off”. This only occurs if the Tx error counter exceeds

a number of 255 errors. Bus-off affects the receiver state. As soon as the transmitter leaves its bus-off state the receiver state

skips to RxOK too. Refer also to TSTAT[1:0] coding in this register.

2 To ensure data integrity, do not read the receive buffer registers while the RXF ﬂag is cleared. For MCUs with dual CPUs,

reading the receive buffer registers while the RXF ﬂag is cleared may result in a CPU fault condition.

76543210

WUPIE

CSCIE

RSTATE1

RSTATE0

TSTATE1

TSTATE0

OVRIE

RXFIE

Reset:

00000000

Figure 12-9. MSCAN Receiver Interrupt Enable Register (CANRIER)

Table 12-9. CANRFLG Register Field Descriptions (continued)

Field

Description

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