MC9S08DZ96F2CLL datasheet(264/458 Pages) FREESCALE

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Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)

MC9S08DZ128 Series Data Sheet, Rev. 1

264

Freescale Semiconductor

NOTE

The CANRFLG register is held in the reset state1 when the initialization

mode is active (INITRQ = 1 and INITAK = 1). This register is writable again

as soon as the initialization mode is exited (INITRQ = 0 and INITAK = 0).

Read: Anytime

Write: Anytime when out of initialization mode, except RSTAT[1:0] and TSTAT[1:0] ﬂags which are

read-only; write of 1 clears ﬂag; write of 0 is ignored.

1. The RSTAT[1:0], TSTAT[1:0] bits are not affected by initialization mode.

Table 12-9. CANRFLG Register Field Descriptions

Field

Description

WUPIF

Wake-Up Interrupt Flag — If the MSCAN detects CAN bus activity while in sleep mode (see Section 12.5.5.4,

“MSCAN Sleep Mode,”) and WUPE = 1 in CANTCTL0 (see Section 12.3.1, “MSCAN Control Register 0

(CANCTL0)”), the module will set WUPIF. If not masked, a wake-up interrupt is pending while this ﬂag is set.

No wake-up activity observed while in sleep mode

MSCAN detected activity on the CAN bus and requested wake-up

CSCIF

CAN Status Change Interrupt Flag — This ﬂag is set when the MSCAN changes its current CAN bus status

due to the actual value of the transmit error counter (TEC) and the receive error counter (REC). An additional

4-bit (RSTAT[1:0], TSTAT[1:0]) status register, which is split into separate sections for TEC/REC, informs the

system on the actual CAN bus status (see Section 12.3.5, “MSCAN Receiver Interrupt Enable Register

(CANRIER)”). If not masked, an error interrupt is pending while this ﬂag is set. CSCIF provides a blocking

interrupt. That guarantees that the receiver/transmitter status bits (RSTAT/TSTAT) are only updated when no CAN

status change interrupt is pending. If the TECs/RECs change their current value after the CSCIF is asserted,

which would cause an additional state change in the RSTAT/TSTAT bits, these bits keep their status until the

current CSCIF interrupt is cleared again.

No change in CAN bus status occurred since last interrupt

MSCAN changed current CAN bus status

5:4

RSTAT[1:0]

Receiver Status Bits — The values of the error counters control the actual CAN bus status of the MSCAN. As

soon as the status change interrupt ﬂag (CSCIF) is set, these bits indicate the appropriate receiver related CAN

bus status of the MSCAN. The coding for the bits RSTAT1, RSTAT0 is:

RxOK: 0

≤ receive error counter ≤ 96

RxWRN: 96

< receive error counter ≤ 127

RxERR: 127

< receive error counter

Bus-off1: transmit error counter

> 255

3:2

TSTAT[1:0]

Transmitter Status Bits — The values of the error counters control the actual CAN bus status of the MSCAN.

As soon as the status change interrupt ﬂag (CSCIF) is set, these bits indicate the appropriate transmitter related

CAN bus status of the MSCAN. The coding for the bits TSTAT1, TSTAT0 is:

TxOK: 0

≤ transmit error counter ≤ 96

TxWRN: 96

< transmit error counter ≤ 127

TxERR: 127

< transmit error counter ≤ 255

Bus-Off: transmit error counter

> 255

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