MC9S08DZ96F2CLL datasheet(224/458 Pages) FREESCALE

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Chapter 10 Analog-to-Digital Converter (S08ADC12V1)

MC9S08DZ128 Series Data Sheet, Rev. 1

224

Freescale Semiconductor

When a conversion is aborted, the contents of the data registers, ADCRH and ADCRL, are not altered.

However, they continue to be the values transferred after the completion of the last successful conversion.

If the conversion was aborted by a reset, ADCRH and ADCRL return to their reset states.

10.4.4.4

Power Control

The ADC module remains in its idle state until a conversion is initiated. If ADACK is selected as the

conversion clock source, the ADACK clock generator is also enabled.

Power consumption when active can be reduced by setting ADLPC. This results in a lower maximum value

for fADCK (see the electrical speciﬁcations).

10.4.4.5

Sample Time and Total Conversion Time

The total conversion time depends on the sample time (as determined by ADLSMP), the MCU bus

frequency, the conversion mode (8-bit, 10-bit or 12-bit), and the frequency of the conversion clock (fADCK).

After the module becomes active, sampling of the input begins. ADLSMP selects between short (3.5

ADCK cycles) and long (23.5 ADCK cycles) sample times.When sampling is complete, the converter is

isolated from the input channel and a successive approximation algorithm is performed to determine the

digital value of the analog signal. The result of the conversion is transferred to ADCRH and ADCRL upon

completion of the conversion algorithm.

If the bus frequency is less than the fADCK frequency, precise sample time for continuous conversions

cannot be guaranteed when short sample is enabled (ADLSMP=0). If the bus frequency is less than 1/11th

of the fADCK frequency, precise sample time for continuous conversions cannot be guaranteed when long

sample is enabled (ADLSMP=1).

The maximum total conversion time for different conditions is summarized in Table 10-13.

Table 10-13. Total Conversion Time vs. Control Conditions

Conversion Type

ADICLK

ADLSMP

Max Total Conversion Time

Single or ﬁrst continuous 8-bit

0x, 10

20 ADCK cycles + 5 bus clock cycles

Single or ﬁrst continuous 10-bit or 12-bit

0x, 10

23 ADCK cycles + 5 bus clock cycles

Single or ﬁrst continuous 8-bit

0x, 10

40 ADCK cycles + 5 bus clock cycles

Single or ﬁrst continuous 10-bit or 12-bit

0x, 10

43 ADCK cycles + 5 bus clock cycles

Single or ﬁrst continuous 8-bit

μs + 20 ADCK + 5 bus clock cycles

Single or ﬁrst continuous 10-bit or 12-bit

μs + 23 ADCK + 5 bus clock cycles

Single or ﬁrst continuous 8-bit

μs + 40 ADCK + 5 bus clock cycles

Single or ﬁrst continuous 10-bit or 12-bit

μs + 43 ADCK + 5 bus clock cycles

Subsequent continuous 8-bit;

fBUS > fADCK

17 ADCK cycles

Subsequent continuous 10-bit or 12-bit;

fBUS > fADCK

20 ADCK cycles

Subsequent continuous 8-bit;

fBUS > fADCK/11

37 ADCK cycles

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