AT90SCR100 datasheet(290/433 Pages) ATMEL

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290

TPR0327AY–SMS–30Jan09

AT90SCR100

21.5.4

HSSPICR - HSSPI Control Register

• Bit 2 - STTTO: Start Time-Out

When set (one), this will rearm the time-out timer and start it once the first byte is received

When cleared (zero), no action is performed.

• Bit 1 - RETTO: Rearm Timeout Interrupt Enable Bit

When set (one), this will rearm the time-out timer, giving more time to receive the next byte.

When cleared (zero), no action is performed.

• Bit 0 - CS: SPI CS Bit

When set (one), the HSSPI HSSS pin is set (one).

When cleared (zero), the SPI HSSS pin is cleared (zero).

21.5.5

HSSPISR - HSSPI Status Register

• Bit 4 - DPRAMRDY: DPRAM Ready Bit

When this bit is set (one), the DPRAM is running and operational.

When this bit is cleared (zero), the DPRAM is not available.

• Bit 3 - NSS: NSS Bit

Status of the HSSS pin

• Bit 2 - RXBUFF: Reception Buffer Full Bit

When this bit is set (one), all reception buffers are full.

• Bit 1 - TXBUFE: Transmission Buffer Empty Bit

When this bit is set (one), all transmission buffers are empty.

• Bit 0 - SPICKRDY: SPI Clock Ready Bit

When this bit is set (one), the HSSPI Controller is running and operational.

When this bit is cleared (zero), the HSSPI Controller is not available.

Bit

76543210

$0000DB

-----

STTTO

RETTO

HSSPICR

Read/write

RRRRR

Initial value

00000000

0x00

Bit

$0000D8

DPRAMRDY

NSS

RXBUFF

TXBUFE SPICKRDY

HSSPISR

Read/write

Initial value

0x00

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