AT90SCR100 datasheet(69/433 Pages) ATMEL

69 / 433 page

TPR0327AY–SMS–30Jan09

AT90SCR100

11. External Interrupts

The External Interrupts are triggered by the INT3:0 pin or any of the PCINT31:0 pins. Observe

that, if enabled, the interrupts will trigger even if the INT3:0 or PCINT31:0 pins are configured as

outputs. This feature provides a way of generating a software interrupt.

The Pin change interrupt PCI3 will trigger if any enabled PCINT31:24 pin toggles, Pin change

interrupt PCI2 will trigger if any enabled PCINT23:16 pin toggles, Pin change interrupt PCI1 will

trigger if any enabled PCINT15:8 pin toggles and Pin change interrupt PCI0 will trigger if any

enabled PCINT7:0 toggles. PCMSK3, PCMSK2, PCMSK1 and PCMSK0 Registers control

which pins contribute to the pin change interrupts. Pin change interrupts on PCINT31:0 are

detected asynchronously. This implies that these interrupts can also be used for waking the part

from sleep modes other than Idle mode.

The External Interrupts can be triggered by a falling or rising edge or a low level. This is set up

as indicated in the specification for the External Interrupt Control Registers – EICRA (INT3:0).

When the external interrupt is enabled and is configured as level triggered, the interrupt will trig-

ger as long as the pin is held low. Low level interrupts and the edge interrupt on INT3:0 are

detected asynchronously. This implies that these interrupts can be used for waking the part also

from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle

mode.

Finally, as the INT2 and INT3 pins, are configured to PB0 and PB1 respectively and these port

bits are multiplexed with other outputs, there is a way to use other pins to trigger INT2 and INT3.

These pins are identified INT2b and INT3b (pins PC0 and PC1). Refer to “EIRR – External Inter-

rupt Redirection Register” on page 71 for more information.

11.1

External Interrupt Registers

11.1.1

EICRA – External Interrupt Control Register A

The External Interrupt Control Register A contains control bits for interrupt sense control.

• Bits 7..0 – ISC31, ISC30 – ISC00, ISC00 : External Interrupt 3 - 0 Sense Control Bits

The External Interrupts 3 - 0 are activated by the external pins INT3:0 if the SREG I-flag and the

corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that

activate the interrupts are defined in Table 11-1. Edges on INT3:0 are registered asynchro-

nously. Pulses on INT3:0 pins wider than the minimum pulse width given in Table 11-2 will

generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If a low level

interrupt is selected, the low level must be held until the completion of the currently executing

instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an inter-

rupt request as long as the pin is held low. When changing the ISCn bit, an interrupt can occur.

If a level triggered interrupt is used for wake-up from Power-down, the required

level must be held long enough for the MCU to complete the wake-up to trigger the

level interrupt. If the level disappears before the end of the Start-up Time, the MCU

will still wake up, but no interrupt will be generated. The start-up time is TBD.

Note

Bit

6543210

$000069

ISC31

ISC30

ISC21

ISC20

ISC11

ISC10

ISC01

ISC00

EICRA

Read/write

R/W

Initial value

0x00

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