AT90SCR100 datasheet(43/433 Pages) ATMEL

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TPR0327AY–SMS–30Jan09

AT90SCR100

Power Management and Sleep Modes

Sleep modes enable the application to shut down unused modules in the MCU, thereby saving

power. The AVR provides various sleep modes allowing the user to tailor the power consump-

tion to the application’s requirements.

To enter any of the five sleep modes, the SE bit in the SMCR must be written to logic one and a

SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select

which sleep mode (Idle, Power-down, Power-save, or Standby) will be activated by the SLEEP

instruction. See Table 8-2 for a summary. If an enabled interrupt occurs while the MCU is in a

sleep mode, the MCU wakes up. The MCU is then halted for four cycles in addition to the start-

up time, executes the interrupt routine, and resumes execution from the instruction following

SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up

from sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the

Reset Vector.

Figure 7-1 on page 31 presents the different clock systems in the AT90SCR100, and their distri-

bution. The figure is helpful in selecting an appropriate sleep mode.

8.1

Power Modes Descriptions

8.1.1

Idle Mode

When the SM2:0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode,

stopping the CPU but allowing the peripherals and the interrupt system to continue operating.

This sleep mode basically halts clkCPU and clkFLASH, while allowing the other clocks to run.

Idle mode enables the MCU to wake up from external triggered interrupts as well as internal

ones like the Timer Overflow and USART Transmit Complete interrupts, as shown in Table 8-1.

8.1.2

Power-down Mode

When the SM2:0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-

down mode. In this mode, the external Oscillator is stopped, while the external interrupts, the 2-

wire Serial Interface, and the Watchdog continue operating (if enabled). Only an External Reset,

a coherent communication request on the different communication interface (TWI, USB, HSSPI,

SPI, USART), a card insertion/removal, an external interrupt, a pin change interrupt or a key-

board pin pressed interrupt can wake up the MCU. This sleep mode basically halts all generated

clocks, allowing operation of asynchronous modules only.

Please refer to the section entitled “Important note about: Entering and Leaving

low consumption modes” on page 47, to read important remarks on achieving min-

imum consumption.

When waking up from Power-down or Power-Save mode, there is a delay from

when the wake-up condition occurs to when the wake-up becomes effective. This

allows the clock to restart and become stable after having been stopped. The

wake-up period is defined by the same CKSEL Fuses that define the Reset Time-

out period, as described in Table 7-3 on page 35.

Caution

Note

To obtain a minimum consumption level, don’t forget to stop the DCDC and PLL,

as remarked in section “Important note about: Entering and Leaving low consump-

tion modes” on page 47.

Caution

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