AT90SCR100 datasheet(70/433 Pages) ATMEL

70 / 433 page

TPR0327AY–SMS–30Jan09

AT90SCR100

Therefore, it is recommended to first disable INTn by clearing its Interrupt Enable bit in the

EIMSK Register. Then, the ISCn bit can be changed. Finally, the INTn interrupt flag should be

cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR Register before the

interrupt is re-enabled.

Note:

1. n = 3, 2, 1or 0.

When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt

Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed

11.1.2

EIMSK – External Interrupt Mask Register

• Bits 3..0 – INT3..0 : External Interrupt Request 3 - 0 Enable

When an INT3:0 bit is written to one and the I-bit in the Status Register (SREG) is set (one), the

corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the External

Interrupt Control Register, EICRA, defines whether the external interrupt is activated on rising or

falling edge or level sensed. Activity on any of these pins will trigger an interrupt request even if

the pin is enabled as an output. This provides a way of generating a software interrupt.

11.1.3

EIFR – External Interrupt Flag Register

• Bits 3..0 – INTF3..0 : External Interrupt Flags 3 - 0

When an edge or logic change on the INT3:0 pin triggers an interrupt request, INTF3:0 becomes

set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT3:0 in EIMSK, are

set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine

Table 11-1.

Interrupt Sense Control(1)

ISCn1

ISCn0

Description

The low level of INTn generates an interrupt request.

Any edge of INTn generates asynchronously an interrupt request.

The falling edge of INTn generates asynchronously an interrupt request.

The rising edge of INTn generates asynchronously an interrupt request.

Table 11-2.

Asynchronous External Interrupt Characteristics

Symbol

Parameter

Condition

Min

Typ

Max

Units

tINT

Minimum pulse width for asynchronous

external interrupt

Bit

6543210

0x1D (0x3D)

----

INT3

INT2

INT1

INT0

EIMSK

Read/write

RRRR

R/W

Initial value

0x00

Bit

6543210

0x1C (0x3C)

----

INTF3

INTF2

INTF1

INTF0

EIFR

Read/write

RRRR

R/W

Initial value

0x00

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