AT90SCR100 datasheet(26/433 Pages) ATMEL

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TPR0327AY–SMS–30Jan09

AT90SCR100

ing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be

omitted. See “Memory Programming” on page 377 for details about Boot programming.

When the write access time has elapsed, the EEPE bit is cleared by hardware. The user soft-

ware can poll this bit and wait for a zero before writing the next byte. When EEPE has been set,

the CPU is halted for two cycles before the next instruction is executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct

address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the

EEPROM read. The EEPROM read access takes one instruction, and the requested data is

available immediately. When the EEPROM is read, the CPU is halted for four cycles before the

next instruction is executed.

The user should poll the EEPE bit before starting the read operation. If a write operation is in

progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.

The calibrated Oscillator is used to time the EEPROM accesses. Table 6-2 lists the typical pro-

gramming time for EEPROM access from the CPU.

6.3.5

Code Examples for EEPROM manipulation

The following code examples show one assembly and one C function for writing to the

EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts glob-

ally) so that no interrupts will occur during execution of these functions. The examples also

assume that no Flash Boot Loader is present in the software. If such code is present, the

EEPROM write function must also wait for any ongoing SPM command to finish.

An interrupt between step 5 and step 6 will make the write cycle fail, since the

EEPROM Master Write Enable will time-out. If an interrupt routine accessing the

EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register

will be modified, causing the interrupted EEPROM access to fail. It is recom-

mended that the Global Interrupt Flag is cleared during all the steps to avoid these

problems.

Table 6-2.

EEPROM Programming Time

Symbol

Number of Calibrated RC Oscillator Cycles

Typ Programming Time

EEPROM write

(from CPU)

26,368 TBC

3.3 ms TBC

Caution

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