AT90SCR100 datasheet(288/433 Pages) ATMEL

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288

TPR0327AY–SMS–30Jan09

AT90SCR100

The CPHA functionality is summarized below:

• Bit 2 - HSCPOL: High Speed Clock POLarity Bit

When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low

when idle. Refer to Figure 21-9 and Figure 21-10.

The CPOL functionality is summarized below:

• Bit 1 - HSMSTR: High Speed Master/Slave Select Bit

This bit selects the Master HSSPI mode when set (one), and Slave HSSPI mode when cleared

(zero).

This bit is cleared by software or by hardware when the HSSPICFG.SPIEN gets cleared (dis-

abling the HSSPI).

• Bit 0 - HSSPIEN: High Speed SPI Enable Bit

When this bit is set (one), the HSSPI Controller is enabled with the predefined configuration.

When this bit is cleared (zero), the HSSPI Controller is disabled and HSSPICFG.HSMSTR is

driven low.

21.5.2

HSSPIIR - HSSPI Interrupt Register

• Bit 7 - TIMEOUT: Timeout Interrupt Bit

This bit is set (one) when a Timeout occurs. An interrupt is generated if HSSPIIER.TIMEOUTIE

is set and global interrupt is enabled.

This bit is cleared by software or by hardware when the HSSPICFG.SPIEN is toggled (enabling

or disabling the HSSPI).

• Bit 6 - BTD: Byte Transfer Done Bit

Table 21-3.

CPHA Configuration

CPHA

Leading edge

Trailing edge

Sample

Setup

1Setup

Sample

Table 21-4.

CPOL Configuration

CPOL

Leading edge

Trailing edge

Rising

Falling

Rising

Configuring and activating the HSSPI peripheral with the same instruction is a valid

action.

Note

Bit

7654

$0000DA

TIMEOUT

BTD

RCVOF

NSSRE

NSSFE

HSSPIIR

Read/write

R/W

Initial value

0000

0x00

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