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AT90SCR100 bảng dữ liệu(PDF) 282 Page - ATMEL Corporation

tên linh kiện AT90SCR100
Giải thích chi tiết về linh kiện  8-bit Microcontroller for Smart Card Readers
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AT90SCR100 bảng dữ liệu(HTML) 282 Page - ATMEL Corporation

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TPR0327AY–SMS–30Jan09
AT90SCR100
21.2.2.2
Buffer sending with DPRAM and HSSPIDMA (DPRAM mode)
When the DPRAM is activated (HSSPICFG.DPRAM bit set), the data to be sent must be written
to one of the internal DPRAM buffers using HSSPIDMA. Once this is done, the number of bytes
to be transmitted is written to the HSSPICNT register. When the master applies the clock, this
number of bytes is shifted from the master to the slave and from the slave to the master simulta-
neously. At this point, new data can be stored in the second buffer if the HSSPISR.TXBUFE = 1.
Each time all the data in one of the buffers is sent, the Byte Transfer Done flag (HSSPIIR.BTD)
is set. If global interrupt and the HSSPIIER.BTDIE bit have been previously set, an interrupt is
generated.
At this stage, the incoming data can be copied from internal DPRAM to RAM using HSSPIDMA.
The HSSPIIR.BTD flag must then be cleared by software.
If the HSSPIIR.BTD is set and the next buffer becomes full, the HSSPIIR.RCVOF is set. If global
interrupt and the HSSPIIER.RCVOFIE bit have been previously set, an interrupt is generated.
The figures below (Figure 21-6, Figure 21-7 & Figure 21-8) illustrate the way the SPI works
when configured as a Slave with DPRAM mode.



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