AT90SCR100 datasheet(277/433 Pages) ATMEL

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277

TPR0327AY–SMS–30Jan09

AT90SCR100

21. High-Speed SPI Controller

This High Speed SPI (HSSPI) Interface comes with 4 dedicated pads (HSMISO, HSMOSI,

HSSCK, HSSS).

21.1

Features

• Support clock up to 20Mhz in Master and Slave Mode

• Full-duplex, 4-wire Synchronous Data Transfer

• Master or Slave Operation

• Transmission / Reception

• Three sources of Interrupt: Byte Transmitted, Time-out and Reception Overflow

• Specific DMA for fast copy from internal DPRAM to RAM

• 4 DPRAM buffers of 16 bytes each: 2 for Reception and 2 for Transmission

• Internal Double Buffering for high performance

• Programmable clock and inter-bytes (guardtime) delays

Figure 21-1.

HSSPI Block Diagram

21.2

Description

The interconnection between Master and Slave CPUs with HSSPI is shown in Figure 21-2.

The HSSPI Controller is enabled by setting the HSSPICFG.SPIEN bit (by default, the HSSPI

Controller is in Slave mode) and fully operational when the HSSPISR.SPICKRDY bit is set. To

select the frequency of the HSSPI clock, the HSSPICFG.SPICKDIV bits (described in page 287)

HSSPI Clock (Master)

Msb

Lsb

HSSPI Status Register

HSSPI Control Register

HSSPI Interrupt

Request

HSSPI Controller

DPRAM

Buffer

Clock

Internal

Data Bus

HSMISO

HSMOSI

HSSCK

Msb

Lsb

Rx 8-Bit Shift Register

Tx 8-Bit Shift Register

HSSS

clk

HSSPI

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